From 4cd841dfe4f15bb21e3f0dce7e70c2a5df005670 Mon Sep 17 00:00:00 2001
From: David Daney <david.daney@cavium.com>
Date: Tue, 22 Dec 2015 16:33:51 -0800
Subject: [PATCH] Add lspci support for Enhanced Allocation Capability.

The PCISIG recently added the Enhanced Allocation Capability.  Decode
it in lspci.
---
 lib/header.h   |   8 ++
 ls-caps.c      | 156 ++++++++++++++++++++++++
 tests/cap-ea-1 | 324 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 488 insertions(+)
 create mode 100644 tests/cap-ea-1

diff --git a/lib/header.h b/lib/header.h
index f7cdee7..b8f7dc1 100644
--- a/lib/header.h
+++ b/lib/header.h
@@ -203,6 +203,7 @@
 #define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
 #define  PCI_CAP_ID_SATA	0x12	/* Serial-ATA HBA */
 #define  PCI_CAP_ID_AF		0x13	/* Advanced features of PCI devices integrated in PCIe root cplx */
+#define  PCI_CAP_ID_EA		0x14	/* Enhanced Allocation */
 #define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
 #define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
 #define PCI_CAP_SIZEOF		4
@@ -906,6 +907,13 @@
 #define PCI_SATA_HBA_BARS	4
 #define PCI_SATA_HBA_REG0	8
 
+/* Enhanced Allocation (EA) */
+#define PCI_EA_CAP_TYPE1_SECONDARY	4
+#define PCI_EA_CAP_TYPE1_SUBORDINATE	5
+/* EA Entry header */
+#define PCI_EA_CAP_ENT_WRITABLE	0x40000000	/* Writable: 1 = RW, 0 = HwInit */
+#define PCI_EA_CAP_ENT_ENABLE	0x80000000	/* Enable for this entry */
+
 /*** Definitions of extended capabilities ***/
 
 /* Advanced Error Reporting */
diff --git a/ls-caps.c b/ls-caps.c
index 639f931..7ff6c67 100644
--- a/ls-caps.c
+++ b/ls-caps.c
@@ -1255,6 +1255,159 @@ cap_sata_hba(struct device *d, int where, int cap)
     printf(" BAR??%d\n", bar);
 }
 
+static const char *cap_ea_property(int p, int is_secondary)
+{
+  switch (p) {
+  case 0x00:
+    return "memory space, non-prefetchable";
+  case 0x01:
+    return "memory space, prefetchable";
+  case 0x02:
+    return "I/O space";
+  case 0x03:
+    return "VF memory space, prefetchable";
+  case 0x04:
+    return "VF memory space, non-prefetchable";
+  case 0x05:
+    return "allocation behind bridge, non-prefetchable memory";
+  case 0x06:
+    return "allocation behind bridge, prefetchable memory";
+  case 0x07:
+    return "allocation behind bridge, I/O space";
+  case 0xfd:
+    return "memory space resource unavailable for use";
+  case 0xfe:
+    return "I/O space resource unavailable for use";
+  case 0xff:
+    if (is_secondary)
+      return "entry unavailable for use, PrimaryProperties should be used";
+    else
+      return "entry unavailable for use";
+  default:
+    return NULL;
+  }
+}
+
+static void cap_ea(struct device *d, int where, int cap)
+{
+  int entry;
+  int entry_base = where + 4;
+  int num_entries = BITS(cap, 0, 6);
+  u8 htype = get_conf_byte(d, PCI_HEADER_TYPE) & 0x7f;
+
+  printf("Enhanced Allocation (EA): NumEntries=%u", num_entries);
+  if (htype == PCI_HEADER_TYPE_BRIDGE) {
+    byte fixed_sub, fixed_sec;
+
+    entry_base += 4;
+    if (!config_fetch(d, where + 4, 2)) {
+      printf("\n");
+      return;
+    }
+    fixed_sec = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SECONDARY);
+    fixed_sub = get_conf_byte(d, where + PCI_EA_CAP_TYPE1_SUBORDINATE);
+    printf(", secondary=%d, subordinate=%d", fixed_sec, fixed_sub);
+  }
+  printf("\n");
+  if (verbose < 2)
+    return;
+
+  for (entry = 0; entry < num_entries; entry++) {
+    int max_offset_high_pos, has_base_high, has_max_offset_high;
+    u32 entry_header;
+    u32 base, max_offset;
+    int es, bei, pp, sp;
+    const char *prop_text;
+
+    if (!config_fetch(d, entry_base, 4))
+      return;
+    entry_header = get_conf_long(d, entry_base);
+    es = BITS(entry_header, 0, 3);
+    bei = BITS(entry_header, 4, 4);
+    pp = BITS(entry_header, 8, 8);
+    sp = BITS(entry_header, 16, 8);
+    if (!config_fetch(d, entry_base + 4, es * 4))
+      return;
+    printf("\t\tEntry %u: Enable%c Writable%c EntrySize=%u\n", entry,
+	   FLAG(entry_header, PCI_EA_CAP_ENT_ENABLE),
+	   FLAG(entry_header, PCI_EA_CAP_ENT_WRITABLE), es);
+    printf("\t\t\t BAR Equivalent Indicator: ");
+    switch (bei) {
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+    case 4:
+    case 5:
+      printf("BAR %u", bei);
+      break;
+    case 6:
+      printf("resource behind function");
+      break;
+    case 7:
+      printf("not indicated");
+      break;
+    case 8:
+      printf("expansion ROM");
+      break;
+    case 9:
+    case 10:
+    case 11:
+    case 12:
+    case 13:
+    case 14:
+      printf("VF-BAR %u", bei - 9);
+      break;
+    default:
+      printf("reserved");
+      break;
+    }
+    printf("\n");
+
+    prop_text = cap_ea_property(pp, 0);
+    printf("\t\t\t PrimaryProperties: ");
+    if (prop_text)
+      printf("%s\n", prop_text);
+    else
+      printf("[%02x]\n", pp);
+
+    prop_text = cap_ea_property(sp, 1);
+    printf("\t\t\t SecondaryProperties: ");
+    if (prop_text)
+      printf("%s\n", prop_text);
+    else
+      printf("[%02x]\n", sp);
+
+    base = get_conf_long(d, entry_base + 4);
+    has_base_high = ((base & 2) != 0);
+    base &= ~3;
+
+    max_offset = get_conf_long(d, entry_base + 8);
+    has_max_offset_high = ((max_offset & 2) != 0);
+    max_offset |= 3;
+    max_offset_high_pos = entry_base + 12;
+
+    printf("\t\t\t Base: ");
+    if (has_base_high) {
+      u32 base_high = get_conf_long(d, entry_base + 12);
+
+      printf("%x", base_high);
+      max_offset_high_pos += 4;
+    }
+    printf("%08x\n", base);
+
+    printf("\t\t\t MaxOffset: ");
+    if (has_max_offset_high) {
+      u32 max_offset_high = get_conf_long(d, max_offset_high_pos);
+
+      printf("%x", max_offset_high);
+    }
+    printf("%08x\n", max_offset);
+
+    entry_base += 4 + 4 * es;
+  }
+}
+
 void
 show_caps(struct device *d, int where)
 {
@@ -1349,6 +1502,9 @@ show_caps(struct device *d, int where)
 	    case PCI_CAP_ID_AF:
 	      cap_af(d, where);
 	      break;
+	    case PCI_CAP_ID_EA:
+	      cap_ea(d, where, cap);
+	      break;
 	    default:
 	      printf("#%02x [%04x]\n", id, cap);
 	    }
diff --git a/tests/cap-ea-1 b/tests/cap-ea-1
new file mode 100644
index 0000000..df88ba9
--- /dev/null
+++ b/tests/cap-ea-1
@@ -0,0 +1,324 @@
+0002:01:00.0 Ethernet controller: Cavium, Inc. THUNDERX Network Interface Controller (rev 08)
+	Subsystem: Cavium, Inc. Device a11e
+	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
+	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
+	Latency: 0
+	Region 0: [virtual] Memory at 843000000000 (32-bit, non-prefetchable) [size=1G]
+	Region 4: [virtual] Memory at 843060000000 (32-bit, non-prefetchable) [size=1M]
+	Capabilities: [40] Express (v2) Endpoint, MSI 00
+		DevCap:	MaxPayload 128 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us
+			ExtTag- AttnBtn- AttnInd- PwrInd- RBE- FLReset- SlotPowerLimit 0.000W
+		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
+			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
+			MaxPayload 128 bytes, MaxReadReq 128 bytes
+		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
+		LnkCap:	Port #0, Speed unknown, Width x0, ASPM not supported, Exit Latency L0s <64ns, L1 <1us
+			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
+		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk-
+			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
+		LnkSta:	Speed unknown, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
+		DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
+		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
+		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
+			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
+			 Compliance De-emphasis: -6dB
+		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
+			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
+	Capabilities: [80] MSI-X: Enable+ Count=10 Masked-
+		Vector table: BAR=4 offset=00000000
+		PBA: BAR=4 offset=000f0000
+	Capabilities: [98] Enhanced Allocation (EA): NumEntries=4
+		Entry 0: Enable+ Writable- EntrySize=4
+			 BAR Equivalent Indicator: BAR 0
+			 PrimaryProperties: memory space, non-prefetchable
+			 SecondaryProperties: entry unavailable for use, PrimaryProperties should be used
+			 Base: 843000000000
+			 MaxOffset: 03fffffff
+		Entry 1: Enable+ Writable- EntrySize=4
+			 BAR Equivalent Indicator: BAR 4
+			 PrimaryProperties: memory space, non-prefetchable
+			 SecondaryProperties: entry unavailable for use, PrimaryProperties should be used
+			 Base: 843060000000
+			 MaxOffset: 0000fffff
+		Entry 2: Enable+ Writable- EntrySize=4
+			 BAR Equivalent Indicator: VF-BAR 0
+			 PrimaryProperties: VF memory space, non-prefetchable
+			 SecondaryProperties: entry unavailable for use, PrimaryProperties should be used
+			 Base: 8430a0000000
+			 MaxOffset: 0001fffff
+		Entry 3: Enable+ Writable- EntrySize=4
+			 BAR Equivalent Indicator: VF-BAR 4
+			 PrimaryProperties: VF memory space, non-prefetchable
+			 SecondaryProperties: entry unavailable for use, PrimaryProperties should be used
+			 Base: 8430e0000000
+			 MaxOffset: 0001fffff
+	Capabilities: [100 v1] Alternative Routing-ID Interpretation (ARI)
+		ARICap:	MFVC- ACS-, Next Function: 0
+		ARICtl:	MFVC- ACS-, Function Group: 0
+	Capabilities: [108 v1] Vendor Specific Information: ID=00a0 Rev=1 Len=040 <?>
+	Capabilities: [180 v1] Single Root I/O Virtualization (SR-IOV)
+		IOVCap:	Migration-, Interrupt Message Number: 000
+		IOVCtl:	Enable+ Migration- Interrupt- MSE+ ARIHierarchy+
+		IOVSta:	Migration-
+		Initial VFs: 128, Total VFs: 128, Number of VFs: 128, Function Dependency Link: 00
+		VF offset: 1, stride: 1, Device ID: a034
+		Supported Page Size: 00000553, System Page Size: 00000100
+		VF Migration: offset: 00000000, BIR: 0
+	Kernel driver in use: thunder-nic
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-- 
2.39.2