From 4d325fc9cd27c1023b74fc0802288ba45c6aa528 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 24 May 2018 10:39:16 +0200 Subject: [PATCH] 4.16-stable patches added patches: asoc-rockchip-rk3288-hdmi-analog-select-needed-codecs.patch asoc-samsung-i2s-ensure-the-rclk-rate-is-properly-determined.patch asoc-samsung-odroid-fix-32000-sample-rate-handling.patch asoc-topology-create-tlv-data-for-dapm-widgets.patch clk-don-t-show-the-incorrect-clock-phase.patch clk-hisilicon-mark-wdt_mux_p-as-const.patch clk-meson-axg-add-the-fractional-part-of-the-fixed_pll.patch clk-meson-axg-fix-the-od-shift-of-the-sys_pll.patch clk-rockchip-fix-wrong-parent-for-sdmmc-phase-clock-for-rk3228.patch clk-rockchip-prevent-calculating-mmc-phase-if-clock-rate-is-zero.patch clk-samsung-exynos3250-fix-pll-rates.patch clk-samsung-exynos5250-fix-pll-rates.patch clk-samsung-exynos5260-fix-pll-rates.patch clk-samsung-exynos5433-fix-pll-rates.patch clk-samsung-exynos7-fix-pll-rates.patch clk-samsung-s3c2410-fix-pll-rates.patch clk-tegra-fix-pll_u-rate-configuration.patch media-cx23885-override-888-impactvcbe-crystal-frequency.patch media-cx23885-set-subdev-host-data-to-clk_freq-pointer.patch media-cx25821-prevent-out-of-bounds-read-on-array-card.patch media-em28xx-add-hauppauge-solohd-dualhd-bulk-models.patch media-i2c-adv748x-fix-hdmi-field-heights.patch media-lgdt3306a-fix-a-double-kfree-on-i2c-device-remove.patch media-ov5645-add-missing-of_node_put-in-error-path.patch media-s3c-camif-fix-out-of-bounds-array-access.patch media-v4l-vsp1-fix-display-stalls-when-requesting-too-many-inputs.patch media-vb2-fix-videobuf2-to-map-correct-area.patch media-vivid-fix-incorrect-capabilities-for-radio.patch --- ...288-hdmi-analog-select-needed-codecs.patch | 33 ++++++++ ...the-rclk-rate-is-properly-determined.patch | 53 ++++++++++++ ...droid-fix-32000-sample-rate-handling.patch | 78 ++++++++++++++++++ ...ogy-create-tlv-data-for-dapm-widgets.patch | 34 ++++++++ ...don-t-show-the-incorrect-clock-phase.patch | 54 +++++++++++++ ...lk-hisilicon-mark-wdt_mux_p-as-const.patch | 34 ++++++++ ...the-fractional-part-of-the-fixed_pll.patch | 38 +++++++++ ...-axg-fix-the-od-shift-of-the-sys_pll.patch | 32 ++++++++ ...ent-for-sdmmc-phase-clock-for-rk3228.patch | 37 +++++++++ ...ting-mmc-phase-if-clock-rate-is-zero.patch | 64 +++++++++++++++ ...clk-samsung-exynos3250-fix-pll-rates.patch | 55 +++++++++++++ ...clk-samsung-exynos5250-fix-pll-rates.patch | 52 ++++++++++++ ...clk-samsung-exynos5260-fix-pll-rates.patch | 43 ++++++++++ ...clk-samsung-exynos5433-fix-pll-rates.patch | 61 ++++++++++++++ .../clk-samsung-exynos7-fix-pll-rates.patch | 43 ++++++++++ .../clk-samsung-s3c2410-fix-pll-rates.patch | 69 ++++++++++++++++ ...k-tegra-fix-pll_u-rate-configuration.patch | 57 +++++++++++++ ...ide-888-impactvcbe-crystal-frequency.patch | 43 ++++++++++ ...subdev-host-data-to-clk_freq-pointer.patch | 36 +++++++++ ...ent-out-of-bounds-read-on-array-card.patch | 53 ++++++++++++ ...-hauppauge-solohd-dualhd-bulk-models.patch | 81 +++++++++++++++++++ ...a-i2c-adv748x-fix-hdmi-field-heights.patch | 43 ++++++++++ ...-a-double-kfree-on-i2c-device-remove.patch | 38 +++++++++ ...dd-missing-of_node_put-in-error-path.patch | 46 +++++++++++ ...camif-fix-out-of-bounds-array-access.patch | 63 +++++++++++++++ ...alls-when-requesting-too-many-inputs.patch | 41 ++++++++++ ...b2-fix-videobuf2-to-map-correct-area.patch | 40 +++++++++ ...fix-incorrect-capabilities-for-radio.patch | 42 ++++++++++ queue-4.16/series | 28 +++++++ 29 files changed, 1391 insertions(+) create mode 100644 queue-4.16/asoc-rockchip-rk3288-hdmi-analog-select-needed-codecs.patch create mode 100644 queue-4.16/asoc-samsung-i2s-ensure-the-rclk-rate-is-properly-determined.patch create mode 100644 queue-4.16/asoc-samsung-odroid-fix-32000-sample-rate-handling.patch create mode 100644 queue-4.16/asoc-topology-create-tlv-data-for-dapm-widgets.patch create mode 100644 queue-4.16/clk-don-t-show-the-incorrect-clock-phase.patch create mode 100644 queue-4.16/clk-hisilicon-mark-wdt_mux_p-as-const.patch create mode 100644 queue-4.16/clk-meson-axg-add-the-fractional-part-of-the-fixed_pll.patch create mode 100644 queue-4.16/clk-meson-axg-fix-the-od-shift-of-the-sys_pll.patch create mode 100644 queue-4.16/clk-rockchip-fix-wrong-parent-for-sdmmc-phase-clock-for-rk3228.patch create mode 100644 queue-4.16/clk-rockchip-prevent-calculating-mmc-phase-if-clock-rate-is-zero.patch create mode 100644 queue-4.16/clk-samsung-exynos3250-fix-pll-rates.patch create mode 100644 queue-4.16/clk-samsung-exynos5250-fix-pll-rates.patch create mode 100644 queue-4.16/clk-samsung-exynos5260-fix-pll-rates.patch create mode 100644 queue-4.16/clk-samsung-exynos5433-fix-pll-rates.patch create mode 100644 queue-4.16/clk-samsung-exynos7-fix-pll-rates.patch create mode 100644 queue-4.16/clk-samsung-s3c2410-fix-pll-rates.patch create mode 100644 queue-4.16/clk-tegra-fix-pll_u-rate-configuration.patch create mode 100644 queue-4.16/media-cx23885-override-888-impactvcbe-crystal-frequency.patch create mode 100644 queue-4.16/media-cx23885-set-subdev-host-data-to-clk_freq-pointer.patch create mode 100644 queue-4.16/media-cx25821-prevent-out-of-bounds-read-on-array-card.patch create mode 100644 queue-4.16/media-em28xx-add-hauppauge-solohd-dualhd-bulk-models.patch create mode 100644 queue-4.16/media-i2c-adv748x-fix-hdmi-field-heights.patch create mode 100644 queue-4.16/media-lgdt3306a-fix-a-double-kfree-on-i2c-device-remove.patch create mode 100644 queue-4.16/media-ov5645-add-missing-of_node_put-in-error-path.patch create mode 100644 queue-4.16/media-s3c-camif-fix-out-of-bounds-array-access.patch create mode 100644 queue-4.16/media-v4l-vsp1-fix-display-stalls-when-requesting-too-many-inputs.patch create mode 100644 queue-4.16/media-vb2-fix-videobuf2-to-map-correct-area.patch create mode 100644 queue-4.16/media-vivid-fix-incorrect-capabilities-for-radio.patch diff --git a/queue-4.16/asoc-rockchip-rk3288-hdmi-analog-select-needed-codecs.patch b/queue-4.16/asoc-rockchip-rk3288-hdmi-analog-select-needed-codecs.patch new file mode 100644 index 00000000000..1eee5f1bc0a --- /dev/null +++ b/queue-4.16/asoc-rockchip-rk3288-hdmi-analog-select-needed-codecs.patch @@ -0,0 +1,33 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Ezequiel Garcia +Date: Tue, 20 Mar 2018 13:03:31 -0300 +Subject: ASoC: rockchip: rk3288-hdmi-analog: Select needed codecs + +From: Ezequiel Garcia + +[ Upstream commit b1d0db067fbe2598d62b248beea5d705a0ea7642 ] + +The driver does not select all the codec drivers that needs. +Fix it by selecting the analog and HDMI codecs. + +Cc: Sjoerd Simons +Signed-off-by: Ezequiel Garcia +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/rockchip/Kconfig | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/sound/soc/rockchip/Kconfig ++++ b/sound/soc/rockchip/Kconfig +@@ -56,6 +56,9 @@ config SND_SOC_RK3288_HDMI_ANALOG + depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP + select SND_SOC_ROCKCHIP_I2S + select SND_SOC_HDMI_CODEC ++ select SND_SOC_ES8328_I2C ++ select SND_SOC_ES8328_SPI if SPI_MASTER ++ select DRM_DW_HDMI_I2S_AUDIO if DRM_DW_HDMI + help + Say Y or M here if you want to add support for SoC audio on Rockchip + RK3288 boards using an analog output and the built-in HDMI audio. diff --git a/queue-4.16/asoc-samsung-i2s-ensure-the-rclk-rate-is-properly-determined.patch b/queue-4.16/asoc-samsung-i2s-ensure-the-rclk-rate-is-properly-determined.patch new file mode 100644 index 00000000000..09f8e601199 --- /dev/null +++ b/queue-4.16/asoc-samsung-i2s-ensure-the-rclk-rate-is-properly-determined.patch @@ -0,0 +1,53 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Sylwester Nawrocki +Date: Mon, 5 Feb 2018 16:43:56 +0100 +Subject: ASoC: samsung: i2s: Ensure the RCLK rate is properly determined + +From: Sylwester Nawrocki + +[ Upstream commit 647d04f8e07afc7c3b7a42b3ee01a8b28db29631 ] + +If the RCLK mux clock configuration is specified in DT and no set_sysclk() +callback is used in the sound card driver the sclk_srcrate field will remain +set to 0, leading to an incorrect PSR divider setting. +To fix this the frequency value is retrieved from the CLK_I2S_RCLK_SRC clock, +so the actual RCLK mux selection is taken into account. + +Signed-off-by: Sylwester Nawrocki +Acked-by: Krzysztof Kozlowski +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/samsung/i2s.c | 13 +++++++++++-- + 1 file changed, 11 insertions(+), 2 deletions(-) + +--- a/sound/soc/samsung/i2s.c ++++ b/sound/soc/samsung/i2s.c +@@ -656,8 +656,12 @@ static int i2s_set_fmt(struct snd_soc_da + tmp |= mod_slave; + break; + case SND_SOC_DAIFMT_CBS_CFS: +- /* Set default source clock in Master mode */ +- if (i2s->rclk_srcrate == 0) ++ /* ++ * Set default source clock in Master mode, only when the ++ * CLK_I2S_RCLK_SRC clock is not exposed so we ensure any ++ * clock configuration assigned in DT is not overwritten. ++ */ ++ if (i2s->rclk_srcrate == 0 && i2s->clk_data.clks == NULL) + i2s_set_sysclk(dai, SAMSUNG_I2S_RCLKSRC_0, + 0, SND_SOC_CLOCK_IN); + break; +@@ -881,6 +885,11 @@ static int config_setup(struct i2s_dai * + return 0; + + if (!(i2s->quirks & QUIRK_NO_MUXPSR)) { ++ struct clk *rclksrc = i2s->clk_table[CLK_I2S_RCLK_SRC]; ++ ++ if (i2s->rclk_srcrate == 0 && rclksrc && !IS_ERR(rclksrc)) ++ i2s->rclk_srcrate = clk_get_rate(rclksrc); ++ + psr = i2s->rclk_srcrate / i2s->frmclk / rfs; + writel(((psr - 1) << 8) | PSR_PSREN, i2s->addr + I2SPSR); + dev_dbg(&i2s->pdev->dev, diff --git a/queue-4.16/asoc-samsung-odroid-fix-32000-sample-rate-handling.patch b/queue-4.16/asoc-samsung-odroid-fix-32000-sample-rate-handling.patch new file mode 100644 index 00000000000..115b51bd7fa --- /dev/null +++ b/queue-4.16/asoc-samsung-odroid-fix-32000-sample-rate-handling.patch @@ -0,0 +1,78 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Sylwester Nawrocki +Date: Wed, 14 Mar 2018 17:41:13 +0100 +Subject: ASoC: samsung: odroid: Fix 32000 sample rate handling + +From: Sylwester Nawrocki + +[ Upstream commit 1d22c337dc8f3a25638f7262e7bcb5729a34d140 ] + +In case of sample rates lower than 44100 currently there is too low MCLK +frequency set for the CODEC. Playback fails with following errors: + +$ speaker-test -c2 -t sine -f 1500 -l2 -r 32000 + +Sine wave rate is 1500.0000Hz +Rate set to 32000Hz (requested 32000Hz) +Buffer size range from 128 to 131072 +Period size range from 64 to 65536 +Using max buffer size 131072 +Periods = 4 +Unable to set hw params for playback: Invalid argument +Setting of hwparams failed: Invalid argument + +[ 497.883700] max98090 1-0010: Invalid master clock frequency + +To fix this the I2S root clock's frequency is increased, depending +on sampling rate. + +Signed-off-by: Sylwester Nawrocki +Acked-by: Krzysztof Kozlowski +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/samsung/odroid.c | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +--- a/sound/soc/samsung/odroid.c ++++ b/sound/soc/samsung/odroid.c +@@ -36,23 +36,26 @@ static int odroid_card_hw_params(struct + { + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct odroid_priv *priv = snd_soc_card_get_drvdata(rtd->card); +- unsigned int pll_freq, rclk_freq; ++ unsigned int pll_freq, rclk_freq, rfs; + int ret; + + switch (params_rate(params)) { +- case 32000: + case 64000: +- pll_freq = 131072006U; ++ pll_freq = 196608001U; ++ rfs = 384; + break; + case 44100: + case 88200: + case 176400: + pll_freq = 180633609U; ++ rfs = 512; + break; ++ case 32000: + case 48000: + case 96000: + case 192000: + pll_freq = 196608001U; ++ rfs = 512; + break; + default: + return -EINVAL; +@@ -67,7 +70,7 @@ static int odroid_card_hw_params(struct + * frequency values due to the EPLL output frequency not being exact + * multiple of the audio sampling rate. + */ +- rclk_freq = params_rate(params) * 256 + 1; ++ rclk_freq = params_rate(params) * rfs + 1; + + ret = clk_set_rate(priv->sclk_i2s, rclk_freq); + if (ret < 0) diff --git a/queue-4.16/asoc-topology-create-tlv-data-for-dapm-widgets.patch b/queue-4.16/asoc-topology-create-tlv-data-for-dapm-widgets.patch new file mode 100644 index 00000000000..7aece617287 --- /dev/null +++ b/queue-4.16/asoc-topology-create-tlv-data-for-dapm-widgets.patch @@ -0,0 +1,34 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Ranjani Sridharan +Date: Fri, 9 Mar 2018 11:11:17 -0800 +Subject: ASoC: topology: create TLV data for dapm widgets + +From: Ranjani Sridharan + +[ Upstream commit bde8b3887add8368ecf0ca71117baf2fd56a6fc9 ] + +This patch adds the change required to create the TLV data +for dapm widget kcontrols from topology. This also fixes the following +TLV read error shown in amixer while showing the card control contents. +"amixer: Control hw:1 element TLV read error: No such device or address" + +Signed-off-by: Ranjani Sridharan +Signed-off-by: Mark Brown +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/soc-topology.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/sound/soc/soc-topology.c ++++ b/sound/soc/soc-topology.c +@@ -1276,6 +1276,9 @@ static struct snd_kcontrol_new *soc_tplg + kfree(sm); + continue; + } ++ ++ /* create any TLV data */ ++ soc_tplg_create_tlv(tplg, &kc[i], &mc->hdr); + } + return kc; + diff --git a/queue-4.16/clk-don-t-show-the-incorrect-clock-phase.patch b/queue-4.16/clk-don-t-show-the-incorrect-clock-phase.patch new file mode 100644 index 00000000000..d73e95e7feb --- /dev/null +++ b/queue-4.16/clk-don-t-show-the-incorrect-clock-phase.patch @@ -0,0 +1,54 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Shawn Lin +Date: Wed, 14 Mar 2018 08:28:31 +0800 +Subject: clk: Don't show the incorrect clock phase + +From: Shawn Lin + +[ Upstream commit 1f9c63e8de3d7b377c9d74e4a17524cfb60e6384 ] + +It's found that the clock phase output from clk_summary is +wrong compared to the actual phase reading from the register. + +cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample +sdio_sample 0 1 0 50000000 0 -22 + +It exposes an issue that clk core, clk_core_get_phase, always +returns the cached core->phase which should be either updated +by calling clk_set_phase or directly from the first place the +clk was registered. + +When registering the clk, the core->phase geting from ->get_phase() +may return negative value indicating error. This is quite common +since the clk's phase may be highly related to its parent chain, +but it was temporarily orphan when registered, since its parent +chains hadn't be ready at that time, so the clk drivers decide to +return error in this case. However, if no clk_set_phase is called or +maybe the ->set_phase() isn't even implemented, the core->phase would +never be updated. This is wrong, and we should try to update it when +all its parent chains are settled down, like the way of updating clock +rate for that. But it's not deserved to complicate the code now and +just update it anyway when calling clk_core_get_phase, which would be +much simple and enough. + +Signed-off-by: Shawn Lin +Acked-by: Jerome Brunet +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/clk.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -2375,6 +2375,9 @@ static int clk_core_get_phase(struct clk + int ret; + + clk_prepare_lock(); ++ /* Always try to update cached phase if possible */ ++ if (core->ops->get_phase) ++ core->phase = core->ops->get_phase(core->hw); + ret = core->phase; + clk_prepare_unlock(); + diff --git a/queue-4.16/clk-hisilicon-mark-wdt_mux_p-as-const.patch b/queue-4.16/clk-hisilicon-mark-wdt_mux_p-as-const.patch new file mode 100644 index 00000000000..7fb609fb5f5 --- /dev/null +++ b/queue-4.16/clk-hisilicon-mark-wdt_mux_p-as-const.patch @@ -0,0 +1,34 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Arnd Bergmann +Date: Tue, 20 Feb 2018 16:15:21 +0100 +Subject: clk: hisilicon: mark wdt_mux_p[] as const + +From: Arnd Bergmann + +[ Upstream commit df934cbcbff7afbc024bf05f02615917c61f6470 ] + +The symbol is in the __initconst section but not marked init, which +caused a warning when building with LTO. + +This makes it 'const' as was obviously intended. + +Signed-off-by: Arnd Bergmann +Fixes: c80dfd9bf54e ("clk: hisilicon: add CRG driver for Hi3516CV300 SoC") +Signed-off-by: Stephen Boyd +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/hisilicon/crg-hi3516cv300.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/hisilicon/crg-hi3516cv300.c ++++ b/drivers/clk/hisilicon/crg-hi3516cv300.c +@@ -204,7 +204,7 @@ static const struct hisi_crg_funcs hi351 + /* hi3516CV300 sysctrl CRG */ + #define HI3516CV300_SYSCTRL_NR_CLKS 16 + +-static const char *wdt_mux_p[] __initconst = { "3m", "apb" }; ++static const char *const wdt_mux_p[] __initconst = { "3m", "apb" }; + static u32 wdt_mux_table[] = {0, 1}; + + static const struct hisi_mux_clock hi3516cv300_sysctrl_mux_clks[] = { diff --git a/queue-4.16/clk-meson-axg-add-the-fractional-part-of-the-fixed_pll.patch b/queue-4.16/clk-meson-axg-add-the-fractional-part-of-the-fixed_pll.patch new file mode 100644 index 00000000000..d000178eef9 --- /dev/null +++ b/queue-4.16/clk-meson-axg-add-the-fractional-part-of-the-fixed_pll.patch @@ -0,0 +1,38 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Jerome Brunet +Date: Fri, 19 Jan 2018 16:55:29 +0100 +Subject: clk: meson: axg: add the fractional part of the fixed_pll + +From: Jerome Brunet + +[ Upstream commit 6b71aceceb09918daf37a40a1221077599040be3 ] + +The fixed_pll also has a fractional part. On axg s400 board, without +this parameter, the calculated rate is off by ~8Mhz (0,4%). The fixed_pll +being the root of the peripheral clock tree, this error is propagated to +the rest of the clocks + +Adding the definition of the parameter fixes the problem + +Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") +Signed-off-by: Jerome Brunet +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/meson/axg.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/clk/meson/axg.c ++++ b/drivers/clk/meson/axg.c +@@ -129,6 +129,11 @@ static struct meson_clk_pll axg_fixed_pl + .shift = 16, + .width = 2, + }, ++ .frac = { ++ .reg_off = HHI_MPLL_CNTL2, ++ .shift = 0, ++ .width = 12, ++ }, + .lock = &meson_clk_lock, + .hw.init = &(struct clk_init_data){ + .name = "fixed_pll", diff --git a/queue-4.16/clk-meson-axg-fix-the-od-shift-of-the-sys_pll.patch b/queue-4.16/clk-meson-axg-fix-the-od-shift-of-the-sys_pll.patch new file mode 100644 index 00000000000..3f4aacdeee9 --- /dev/null +++ b/queue-4.16/clk-meson-axg-fix-the-od-shift-of-the-sys_pll.patch @@ -0,0 +1,32 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Yixun Lan +Date: Fri, 19 Jan 2018 10:09:26 +0800 +Subject: clk: meson: axg: fix the od shift of the sys_pll + +From: Yixun Lan + +[ Upstream commit 2fa9b361e500a0e092a9525afbd6a3a363ffa5f0 ] + +According to the datasheet, the od shift of sys_pll is actually 16. + +Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers') +Signed-off-by: Yixun Lan +[fixed commit message] +Signed-off-by: Jerome Brunet +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/meson/axg.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/meson/axg.c ++++ b/drivers/clk/meson/axg.c +@@ -151,7 +151,7 @@ static struct meson_clk_pll axg_sys_pll + }, + .od = { + .reg_off = HHI_SYS_PLL_CNTL, +- .shift = 10, ++ .shift = 16, + .width = 2, + }, + .rate_table = sys_pll_rate_table, diff --git a/queue-4.16/clk-rockchip-fix-wrong-parent-for-sdmmc-phase-clock-for-rk3228.patch b/queue-4.16/clk-rockchip-fix-wrong-parent-for-sdmmc-phase-clock-for-rk3228.patch new file mode 100644 index 00000000000..6fe3a7a7f45 --- /dev/null +++ b/queue-4.16/clk-rockchip-fix-wrong-parent-for-sdmmc-phase-clock-for-rk3228.patch @@ -0,0 +1,37 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Shawn Lin +Date: Wed, 21 Mar 2018 10:39:19 +0800 +Subject: clk: rockchip: Fix wrong parent for SDMMC phase clock for rk3228 + +From: Shawn Lin + +[ Upstream commit 4b0556a441dd37e598887215bc89b49a6ef525b3 ] + +commit c420c1e4db22 ("clk: rockchip: Prevent calculating mmc phase +if clock rate is zero") catches one gremlin again for clk-rk3228.c +that the parent of SDMMC phase clock should be sclk_sdmmc0, but not +sclk_sdmmc. However, the naming of the sdmmc clocks varies in the +manual with the card clock having the 0 while the hclk is named +without appended 0. So standardize one one format to prevent +confusion, as there also is only one (non-sdio) mmc controller on +the soc. + +Signed-off-by: Shawn Lin +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/rockchip/clk-rk3228.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/rockchip/clk-rk3228.c ++++ b/drivers/clk/rockchip/clk-rk3228.c +@@ -387,7 +387,7 @@ static struct rockchip_clk_branch rk3228 + RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS, + RK2928_CLKGATE_CON(2), 15, GFLAGS), + +- COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0, ++ COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0, + RK2928_CLKSEL_CON(11), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK2928_CLKGATE_CON(2), 11, GFLAGS), + diff --git a/queue-4.16/clk-rockchip-prevent-calculating-mmc-phase-if-clock-rate-is-zero.patch b/queue-4.16/clk-rockchip-prevent-calculating-mmc-phase-if-clock-rate-is-zero.patch new file mode 100644 index 00000000000..380d343eace --- /dev/null +++ b/queue-4.16/clk-rockchip-prevent-calculating-mmc-phase-if-clock-rate-is-zero.patch @@ -0,0 +1,64 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Shawn Lin +Date: Mon, 5 Mar 2018 11:25:58 +0800 +Subject: clk: rockchip: Prevent calculating mmc phase if clock rate is zero + +From: Shawn Lin + +[ Upstream commit 4bf59902b50012b1dddeeaa23b217d9c4956cdda ] + +The MMC sample and drv clock for rockchip platforms are derived from +the bus clock output to the MMC/SDIO card. So it should never happens +that the clk rate is zero given it should inherits the clock rate from +its parent. If something goes wrong and makes the clock rate to be zero, +the calculation would be wrong but may still make the mmc tuning process +work luckily. However it makes people harder to debug when the following +data transfer is unstable. + +Signed-off-by: Shawn Lin +Signed-off-by: Heiko Stuebner +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/rockchip/clk-mmc-phase.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/clk/rockchip/clk-mmc-phase.c ++++ b/drivers/clk/rockchip/clk-mmc-phase.c +@@ -58,6 +58,12 @@ static int rockchip_mmc_get_phase(struct + u16 degrees; + u32 delay_num = 0; + ++ /* See the comment for rockchip_mmc_set_phase below */ ++ if (!rate) { ++ pr_err("%s: invalid clk rate\n", __func__); ++ return -EINVAL; ++ } ++ + raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); + + degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90; +@@ -84,6 +90,23 @@ static int rockchip_mmc_set_phase(struct + u32 raw_value; + u32 delay; + ++ /* ++ * The below calculation is based on the output clock from ++ * MMC host to the card, which expects the phase clock inherits ++ * the clock rate from its parent, namely the output clock ++ * provider of MMC host. However, things may go wrong if ++ * (1) It is orphan. ++ * (2) It is assigned to the wrong parent. ++ * ++ * This check help debug the case (1), which seems to be the ++ * most likely problem we often face and which makes it difficult ++ * for people to debug unstable mmc tuning results. ++ */ ++ if (!rate) { ++ pr_err("%s: invalid clk rate\n", __func__); ++ return -EINVAL; ++ } ++ + nineties = degrees / 90; + remainder = (degrees % 90); + diff --git a/queue-4.16/clk-samsung-exynos3250-fix-pll-rates.patch b/queue-4.16/clk-samsung-exynos3250-fix-pll-rates.patch new file mode 100644 index 00000000000..83cb338d92a --- /dev/null +++ b/queue-4.16/clk-samsung-exynos3250-fix-pll-rates.patch @@ -0,0 +1,55 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Andrzej Hajda +Date: Fri, 16 Feb 2018 15:57:48 +0100 +Subject: clk: samsung: exynos3250: Fix PLL rates + +From: Andrzej Hajda + +[ Upstream commit a8321e7887410a2b2e80ab89d1ef7b30562658ea ] + +Rates declared in PLL rate tables should match exactly rates calculated +from PLL coefficients. If that is not the case, rate of the PLL's child clock +might be set not as expected. For instance, if in the PLL rates table we have +a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate +callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate +will return 393216003. If we now attempt to set rate of a PLL's child divider +clock to 393216000/2 its rate will be 131072001, rather than 196608000. +That is, the divider will be set to 3 instead of 2, because 393216003/2 is +greater than 196608000. + +To fix this issue declared rates are changed to exactly match rates generated +by the PLL, as calculated from the P, M, S, K coefficients. + +In this patch an erroneous P value for 74176002 output frequency is also +corrected. + +Signed-off-by: Andrzej Hajda +Acked-by: Chanwoo Choi +Acked-by: Tomasz Figa +Signed-off-by: Sylwester Nawrocki +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/samsung/clk-exynos3250.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/clk/samsung/clk-exynos3250.c ++++ b/drivers/clk/samsung/clk-exynos3250.c +@@ -698,7 +698,7 @@ static const struct samsung_pll_rate_tab + PLL_36XX_RATE(144000000, 96, 2, 3, 0), + PLL_36XX_RATE( 96000000, 128, 2, 4, 0), + PLL_36XX_RATE( 84000000, 112, 2, 4, 0), +- PLL_36XX_RATE( 80000004, 106, 2, 4, 43691), ++ PLL_36XX_RATE( 80000003, 106, 2, 4, 43691), + PLL_36XX_RATE( 73728000, 98, 2, 4, 19923), + PLL_36XX_RATE( 67737598, 270, 3, 5, 62285), + PLL_36XX_RATE( 65535999, 174, 2, 5, 49982), +@@ -734,7 +734,7 @@ static const struct samsung_pll_rate_tab + PLL_36XX_RATE(148352005, 98, 2, 3, 59070), + PLL_36XX_RATE(108000000, 144, 2, 4, 0), + PLL_36XX_RATE( 74250000, 99, 2, 4, 0), +- PLL_36XX_RATE( 74176002, 98, 3, 4, 59070), ++ PLL_36XX_RATE( 74176002, 98, 2, 4, 59070), + PLL_36XX_RATE( 54054000, 216, 3, 5, 14156), + PLL_36XX_RATE( 54000000, 144, 2, 5, 0), + { /* sentinel */ } diff --git a/queue-4.16/clk-samsung-exynos5250-fix-pll-rates.patch b/queue-4.16/clk-samsung-exynos5250-fix-pll-rates.patch new file mode 100644 index 00000000000..b31f766c09a --- /dev/null +++ b/queue-4.16/clk-samsung-exynos5250-fix-pll-rates.patch @@ -0,0 +1,52 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Andrzej Hajda +Date: Fri, 16 Feb 2018 15:57:49 +0100 +Subject: clk: samsung: exynos5250: Fix PLL rates + +From: Andrzej Hajda + +[ Upstream commit 2ac051eeabaa411ef89ae7cd5bb8e60cb41ad780 ] + +Rates declared in PLL rate tables should match exactly rates calculated +from PLL coefficients. If that is not the case, rate of the PLL's child clock +might be set not as expected. For instance, if in the PLL rates table we have +a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate +callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate +will return 393216003. If we now attempt to set rate of a PLL's child divider +clock to 393216000/2 its rate will be 131072001, rather than 196608000. +That is, the divider will be set to 3 instead of 2, because 393216003/2 is +greater than 196608000. + +To fix this issue declared rates are changed to exactly match rates generated +by the PLL, as calculated from the P, M, S, K coefficients. + +Signed-off-by: Andrzej Hajda +Acked-by: Chanwoo Choi +Acked-by: Tomasz Figa +Signed-off-by: Sylwester Nawrocki +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/samsung/clk-exynos5250.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/clk/samsung/clk-exynos5250.c ++++ b/drivers/clk/samsung/clk-exynos5250.c +@@ -711,13 +711,13 @@ static const struct samsung_pll_rate_tab + /* sorted in descending order */ + /* PLL_36XX_RATE(rate, m, p, s, k) */ + PLL_36XX_RATE(192000000, 64, 2, 2, 0), +- PLL_36XX_RATE(180633600, 90, 3, 2, 20762), ++ PLL_36XX_RATE(180633605, 90, 3, 2, 20762), + PLL_36XX_RATE(180000000, 90, 3, 2, 0), + PLL_36XX_RATE(73728000, 98, 2, 4, 19923), +- PLL_36XX_RATE(67737600, 90, 2, 4, 20762), ++ PLL_36XX_RATE(67737602, 90, 2, 4, 20762), + PLL_36XX_RATE(49152000, 98, 3, 4, 19923), +- PLL_36XX_RATE(45158400, 90, 3, 4, 20762), +- PLL_36XX_RATE(32768000, 131, 3, 5, 4719), ++ PLL_36XX_RATE(45158401, 90, 3, 4, 20762), ++ PLL_36XX_RATE(32768001, 131, 3, 5, 4719), + { }, + }; + diff --git a/queue-4.16/clk-samsung-exynos5260-fix-pll-rates.patch b/queue-4.16/clk-samsung-exynos5260-fix-pll-rates.patch new file mode 100644 index 00000000000..5e8e96f9aea --- /dev/null +++ b/queue-4.16/clk-samsung-exynos5260-fix-pll-rates.patch @@ -0,0 +1,43 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Andrzej Hajda +Date: Fri, 16 Feb 2018 15:57:50 +0100 +Subject: clk: samsung: exynos5260: Fix PLL rates + +From: Andrzej Hajda + +[ Upstream commit cdb68fbd4e7962be742c4f29475220c5bf28d8a5 ] + +Rates declared in PLL rate tables should match exactly rates calculated from +the PLL coefficients. If that is not the case, rate of the PLL's child clock +might be set not as expected. For instance, if in the PLL rates table we have +a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate +callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate +will return 393216003. If we now attempt to set rate of a PLL's child divider +clock to 393216000/2 its rate will be 131072001, rather than 196608000. +That is, the divider will be set to 3 instead of 2, because 393216003/2 is +greater than 196608000. + +To fix this issue declared rates are changed to exactly match rates generated +by the PLL, as calculated from the P, M, S, K coefficients. + +Signed-off-by: Andrzej Hajda +Acked-by: Tomasz Figa +Acked-by: Chanwoo Choi +Signed-off-by: Sylwester Nawrocki +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/samsung/clk-exynos5260.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/samsung/clk-exynos5260.c ++++ b/drivers/clk/samsung/clk-exynos5260.c +@@ -65,7 +65,7 @@ static const struct samsung_pll_rate_tab + PLL_36XX_RATE(480000000, 160, 2, 2, 0), + PLL_36XX_RATE(432000000, 144, 2, 2, 0), + PLL_36XX_RATE(400000000, 200, 3, 2, 0), +- PLL_36XX_RATE(394073130, 459, 7, 2, 49282), ++ PLL_36XX_RATE(394073128, 459, 7, 2, 49282), + PLL_36XX_RATE(333000000, 111, 2, 2, 0), + PLL_36XX_RATE(300000000, 100, 2, 2, 0), + PLL_36XX_RATE(266000000, 266, 3, 3, 0), diff --git a/queue-4.16/clk-samsung-exynos5433-fix-pll-rates.patch b/queue-4.16/clk-samsung-exynos5433-fix-pll-rates.patch new file mode 100644 index 00000000000..25a02199d32 --- /dev/null +++ b/queue-4.16/clk-samsung-exynos5433-fix-pll-rates.patch @@ -0,0 +1,61 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Andrzej Hajda +Date: Fri, 16 Feb 2018 15:57:51 +0100 +Subject: clk: samsung: exynos5433: Fix PLL rates + +From: Andrzej Hajda + +[ Upstream commit ab0447845cffc0fd752df2ccd6b4e34006000ce4 ] + +Rates declared in PLL rate tables should match exactly rates calculated from +the PLL coefficients. If that is not the case, rate of the PLL's child clock +might be set not as expected. For instance, if in the PLL rates table we have +a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate +callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate +will return 393216003. If we now attempt to set rate of a PLL's child divider +clock to 393216000/2 its rate will be 131072001, rather than 196608000. +That is, the divider will be set to 3 instead of 2, because 393216003/2 is +greater than 196608000. + +To fix this issue declared rates are changed to exactly match rates generated +by the PLL, as calculated from the P, M, S, K coefficients. + +Signed-off-by: Andrzej Hajda +Acked-by: Tomasz Figa +Acked-by: Chanwoo Choi +Signed-off-by: Sylwester Nawrocki +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/samsung/clk-exynos5433.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/clk/samsung/clk-exynos5433.c ++++ b/drivers/clk/samsung/clk-exynos5433.c +@@ -729,7 +729,7 @@ static const struct samsung_pll_rate_tab + PLL_35XX_RATE(800000000U, 400, 6, 1), + PLL_35XX_RATE(733000000U, 733, 12, 1), + PLL_35XX_RATE(700000000U, 175, 3, 1), +- PLL_35XX_RATE(667000000U, 222, 4, 1), ++ PLL_35XX_RATE(666000000U, 222, 4, 1), + PLL_35XX_RATE(633000000U, 211, 4, 1), + PLL_35XX_RATE(600000000U, 500, 5, 2), + PLL_35XX_RATE(552000000U, 460, 5, 2), +@@ -757,12 +757,12 @@ static const struct samsung_pll_rate_tab + /* AUD_PLL */ + static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = { + PLL_36XX_RATE(400000000U, 200, 3, 2, 0), +- PLL_36XX_RATE(393216000U, 197, 3, 2, -25690), ++ PLL_36XX_RATE(393216003U, 197, 3, 2, -25690), + PLL_36XX_RATE(384000000U, 128, 2, 2, 0), +- PLL_36XX_RATE(368640000U, 246, 4, 2, -15729), +- PLL_36XX_RATE(361507200U, 181, 3, 2, -16148), +- PLL_36XX_RATE(338688000U, 113, 2, 2, -6816), +- PLL_36XX_RATE(294912000U, 98, 1, 3, 19923), ++ PLL_36XX_RATE(368639991U, 246, 4, 2, -15729), ++ PLL_36XX_RATE(361507202U, 181, 3, 2, -16148), ++ PLL_36XX_RATE(338687988U, 113, 2, 2, -6816), ++ PLL_36XX_RATE(294912002U, 98, 1, 3, 19923), + PLL_36XX_RATE(288000000U, 96, 1, 3, 0), + PLL_36XX_RATE(252000000U, 84, 1, 3, 0), + { /* sentinel */ } diff --git a/queue-4.16/clk-samsung-exynos7-fix-pll-rates.patch b/queue-4.16/clk-samsung-exynos7-fix-pll-rates.patch new file mode 100644 index 00000000000..b7455d00e9e --- /dev/null +++ b/queue-4.16/clk-samsung-exynos7-fix-pll-rates.patch @@ -0,0 +1,43 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Andrzej Hajda +Date: Fri, 16 Feb 2018 15:57:52 +0100 +Subject: clk: samsung: exynos7: Fix PLL rates + +From: Andrzej Hajda + +[ Upstream commit 7e4db0c2836e892766565965207eee051c8037b9 ] + +Rates declared in PLL rate tables should match exactly rates calculated from +the PLL coefficients. If that is not the case, rate of the PLL's child clock +might be set not as expected. For instance, if in the PLL rates table we have +a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate +callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate +will return 393216003. If we now attempt to set rate of a PLL's child divider +clock to 393216000/2 its rate will be 131072001, rather than 196608000. +That is, the divider will be set to 3 instead of 2, because 393216003/2 is +greater than 196608000. + +To fix this issue declared rates are changed to exactly match rates generated +by the PLL, as calculated from the P, M, S, K coefficients. + +Signed-off-by: Andrzej Hajda +Acked-by: Tomasz Figa +Acked-by: Chanwoo Choi +Signed-off-by: Sylwester Nawrocki +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/samsung/clk-exynos7.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/samsung/clk-exynos7.c ++++ b/drivers/clk/samsung/clk-exynos7.c +@@ -140,7 +140,7 @@ static const struct samsung_div_clock to + }; + + static const struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initconst = { +- PLL_36XX_RATE(491520000, 20, 1, 0, 31457), ++ PLL_36XX_RATE(491519897, 20, 1, 0, 31457), + {}, + }; + diff --git a/queue-4.16/clk-samsung-s3c2410-fix-pll-rates.patch b/queue-4.16/clk-samsung-s3c2410-fix-pll-rates.patch new file mode 100644 index 00000000000..8b9748449e7 --- /dev/null +++ b/queue-4.16/clk-samsung-s3c2410-fix-pll-rates.patch @@ -0,0 +1,69 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Andrzej Hajda +Date: Fri, 16 Feb 2018 15:57:53 +0100 +Subject: clk: samsung: s3c2410: Fix PLL rates + +From: Andrzej Hajda + +[ Upstream commit 179db533c08431f509a3823077549773d519358b ] + +Rates declared in PLL rate tables should match exactly rates calculated from +the PLL coefficients. If that is not the case, rate of the PLL's child clock +might be set not as expected. For instance, if in the PLL rates table we have +a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate +callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate +will return 393216003. If we now attempt to set rate of a PLL's child divider +clock to 393216000/2 its rate will be 131072001, rather than 196608000. +That is, the divider will be set to 3 instead of 2, because 393216003/2 is +greater than 196608000. + +To fix this issue declared rates are changed to exactly match rates generated +by the PLL, as calculated from the P, M, S, K coefficients. + +Signed-off-by: Andrzej Hajda +Acked-by: Tomasz Figa +Acked-by: Chanwoo Choi +Signed-off-by: Sylwester Nawrocki +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/samsung/clk-s3c2410.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +--- a/drivers/clk/samsung/clk-s3c2410.c ++++ b/drivers/clk/samsung/clk-s3c2410.c +@@ -168,7 +168,7 @@ static struct samsung_pll_rate_table pll + PLL_35XX_RATE(226000000, 105, 1, 1), + PLL_35XX_RATE(210000000, 132, 2, 1), + /* 2410 common */ +- PLL_35XX_RATE(203000000, 161, 3, 1), ++ PLL_35XX_RATE(202800000, 161, 3, 1), + PLL_35XX_RATE(192000000, 88, 1, 1), + PLL_35XX_RATE(186000000, 85, 1, 1), + PLL_35XX_RATE(180000000, 82, 1, 1), +@@ -178,18 +178,18 @@ static struct samsung_pll_rate_table pll + PLL_35XX_RATE(147000000, 90, 2, 1), + PLL_35XX_RATE(135000000, 82, 2, 1), + PLL_35XX_RATE(124000000, 116, 1, 2), +- PLL_35XX_RATE(118000000, 150, 2, 2), ++ PLL_35XX_RATE(118500000, 150, 2, 2), + PLL_35XX_RATE(113000000, 105, 1, 2), +- PLL_35XX_RATE(101000000, 127, 2, 2), ++ PLL_35XX_RATE(101250000, 127, 2, 2), + PLL_35XX_RATE(90000000, 112, 2, 2), +- PLL_35XX_RATE(85000000, 105, 2, 2), ++ PLL_35XX_RATE(84750000, 105, 2, 2), + PLL_35XX_RATE(79000000, 71, 1, 2), +- PLL_35XX_RATE(68000000, 82, 2, 2), +- PLL_35XX_RATE(56000000, 142, 2, 3), ++ PLL_35XX_RATE(67500000, 82, 2, 2), ++ PLL_35XX_RATE(56250000, 142, 2, 3), + PLL_35XX_RATE(48000000, 120, 2, 3), +- PLL_35XX_RATE(51000000, 161, 3, 3), ++ PLL_35XX_RATE(50700000, 161, 3, 3), + PLL_35XX_RATE(45000000, 82, 1, 3), +- PLL_35XX_RATE(34000000, 82, 2, 3), ++ PLL_35XX_RATE(33750000, 82, 2, 3), + { /* sentinel */ }, + }; + diff --git a/queue-4.16/clk-tegra-fix-pll_u-rate-configuration.patch b/queue-4.16/clk-tegra-fix-pll_u-rate-configuration.patch new file mode 100644 index 00000000000..2d8b75f0932 --- /dev/null +++ b/queue-4.16/clk-tegra-fix-pll_u-rate-configuration.patch @@ -0,0 +1,57 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Marcel Ziswiler +Date: Fri, 23 Feb 2018 00:04:51 +0100 +Subject: clk: tegra: Fix pll_u rate configuration + +From: Marcel Ziswiler + +[ Upstream commit c35b518f9ba06c9de79fb3ff62eed7462d804995 ] + +Turns out latest upstream U-Boot does not configure/enable pll_u which +leaves it at some default rate of 500 kHz: + +root@apalis-t30:~# cat /sys/kernel/debug/clk/clk_summary | grep pll_u + pll_u 3 3 0 500000 0 + +Of course this won't quite work leading to the following messages: + +[ 6.559593] usb 2-1: new full-speed USB device number 2 using tegra- +ehci +[ 11.759173] usb 2-1: device descriptor read/64, error -110 +[ 27.119453] usb 2-1: device descriptor read/64, error -110 +[ 27.389217] usb 2-1: new full-speed USB device number 3 using tegra- +ehci +[ 32.559454] usb 2-1: device descriptor read/64, error -110 +[ 47.929777] usb 2-1: device descriptor read/64, error -110 +[ 48.049658] usb usb2-port1: attempt power cycle +[ 48.759475] usb 2-1: new full-speed USB device number 4 using tegra- +ehci +[ 59.349457] usb 2-1: device not accepting address 4, error -110 +[ 59.509449] usb 2-1: new full-speed USB device number 5 using tegra- +ehci +[ 70.069457] usb 2-1: device not accepting address 5, error -110 +[ 70.079721] usb usb2-port1: unable to enumerate USB device + +Fix this by actually allowing the rate also being set from within +the Linux kernel. + +Signed-off-by: Marcel Ziswiler +Tested-by: Jon Hunter +Signed-off-by: Thierry Reding +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/clk/tegra/clk-pll.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/clk/tegra/clk-pll.c ++++ b/drivers/clk/tegra/clk-pll.c +@@ -1151,6 +1151,8 @@ static const struct clk_ops tegra_clk_pl + .enable = clk_pllu_enable, + .disable = clk_pll_disable, + .recalc_rate = clk_pll_recalc_rate, ++ .round_rate = clk_pll_round_rate, ++ .set_rate = clk_pll_set_rate, + }; + + static int _pll_fixed_mdiv(struct tegra_clk_pll_params *pll_params, diff --git a/queue-4.16/media-cx23885-override-888-impactvcbe-crystal-frequency.patch b/queue-4.16/media-cx23885-override-888-impactvcbe-crystal-frequency.patch new file mode 100644 index 00000000000..c9037e6719e --- /dev/null +++ b/queue-4.16/media-cx23885-override-888-impactvcbe-crystal-frequency.patch @@ -0,0 +1,43 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Brad Love +Date: Tue, 6 Mar 2018 14:15:37 -0500 +Subject: media: cx23885: Override 888 ImpactVCBe crystal frequency + +From: Brad Love + +[ Upstream commit 779c79d4b833ec646b0aed878da38edb45bbe156 ] + +Hauppauge produced a revision of ImpactVCBe using an 888, +with a 25MHz crystal, instead of using the default third +overtone 50Mhz crystal. This overrides that frequency so +that the cx25840 is properly configured. Without the proper +crystal setup the cx25840 cannot load the firmware or +decode video. + +Signed-off-by: Brad Love +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/pci/cx23885/cx23885-core.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/media/pci/cx23885/cx23885-core.c ++++ b/drivers/media/pci/cx23885/cx23885-core.c +@@ -873,6 +873,16 @@ static int cx23885_dev_setup(struct cx23 + if (cx23885_boards[dev->board].clk_freq > 0) + dev->clk_freq = cx23885_boards[dev->board].clk_freq; + ++ if (dev->board == CX23885_BOARD_HAUPPAUGE_IMPACTVCBE && ++ dev->pci->subsystem_device == 0x7137) { ++ /* Hauppauge ImpactVCBe device ID 0x7137 is populated ++ * with an 888, and a 25Mhz crystal, instead of the ++ * usual third overtone 50Mhz. The default clock rate must ++ * be overridden so the cx25840 is properly configured ++ */ ++ dev->clk_freq = 25000000; ++ } ++ + dev->pci_bus = dev->pci->bus->number; + dev->pci_slot = PCI_SLOT(dev->pci->devfn); + cx23885_irq_add(dev, 0x001f00); diff --git a/queue-4.16/media-cx23885-set-subdev-host-data-to-clk_freq-pointer.patch b/queue-4.16/media-cx23885-set-subdev-host-data-to-clk_freq-pointer.patch new file mode 100644 index 00000000000..9b09c78cf55 --- /dev/null +++ b/queue-4.16/media-cx23885-set-subdev-host-data-to-clk_freq-pointer.patch @@ -0,0 +1,36 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Brad Love +Date: Tue, 6 Mar 2018 14:15:36 -0500 +Subject: media: cx23885: Set subdev host data to clk_freq pointer + +From: Brad Love + +[ Upstream commit 5ceade1d97fc6687e050c44c257382c192f56276 ] + +Currently clk_freq is ignored entirely, because the cx235840 driver +configures the xtal at the chip defaults. This is an issue if a +board is produced with a non-default frequency crystal. If clk_freq +is not zero the cx25840 will attempt to use the setting provided, +or fall back to defaults otherwise. + +Signed-off-by: Brad Love +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/pci/cx23885/cx23885-cards.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/media/pci/cx23885/cx23885-cards.c ++++ b/drivers/media/pci/cx23885/cx23885-cards.c +@@ -2286,6 +2286,10 @@ void cx23885_card_setup(struct cx23885_d + &dev->i2c_bus[2].i2c_adap, + "cx25840", 0x88 >> 1, NULL); + if (dev->sd_cx25840) { ++ /* set host data for clk_freq configuration */ ++ v4l2_set_subdev_hostdata(dev->sd_cx25840, ++ &dev->clk_freq); ++ + dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE; + v4l2_subdev_call(dev->sd_cx25840, core, load_fw); + } diff --git a/queue-4.16/media-cx25821-prevent-out-of-bounds-read-on-array-card.patch b/queue-4.16/media-cx25821-prevent-out-of-bounds-read-on-array-card.patch new file mode 100644 index 00000000000..0bbe09e4bfa --- /dev/null +++ b/queue-4.16/media-cx25821-prevent-out-of-bounds-read-on-array-card.patch @@ -0,0 +1,53 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Colin Ian King +Date: Wed, 31 Jan 2018 12:33:09 -0500 +Subject: media: cx25821: prevent out-of-bounds read on array card + +From: Colin Ian King + +[ Upstream commit 67300abdbe9f1717532aaf4e037222762716d0f6 ] + +Currently an out of range dev->nr is detected by just reporting the +issue and later on an out-of-bounds read on array card occurs because +of this. Fix this by checking the upper range of dev->nr with the size +of array card (removes the hard coded size), move this check earlier +and also exit with the error -ENOSYS to avoid the later out-of-bounds +array read. + +Detected by CoverityScan, CID#711191 ("Out-of-bounds-read") + +Fixes: commit 02b20b0b4cde ("V4L/DVB (12730): Add conexant cx25821 driver") + +Signed-off-by: Colin Ian King +Signed-off-by: Hans Verkuil +[hans.verkuil@cisco.com: %ld -> %zd] +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/pci/cx25821/cx25821-core.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/media/pci/cx25821/cx25821-core.c ++++ b/drivers/media/pci/cx25821/cx25821-core.c +@@ -867,6 +867,10 @@ static int cx25821_dev_setup(struct cx25 + dev->nr = ++cx25821_devcount; + sprintf(dev->name, "cx25821[%d]", dev->nr); + ++ if (dev->nr >= ARRAY_SIZE(card)) { ++ CX25821_INFO("dev->nr >= %zd", ARRAY_SIZE(card)); ++ return -ENODEV; ++ } + if (dev->pci->device != 0x8210) { + pr_info("%s(): Exiting. Incorrect Hardware device = 0x%02x\n", + __func__, dev->pci->device); +@@ -882,9 +886,6 @@ static int cx25821_dev_setup(struct cx25 + dev->channels[i].sram_channels = &cx25821_sram_channels[i]; + } + +- if (dev->nr > 1) +- CX25821_INFO("dev->nr > 1!"); +- + /* board config */ + dev->board = 1; /* card[dev->nr]; */ + dev->_max_num_decoders = MAX_DECODERS; diff --git a/queue-4.16/media-em28xx-add-hauppauge-solohd-dualhd-bulk-models.patch b/queue-4.16/media-em28xx-add-hauppauge-solohd-dualhd-bulk-models.patch new file mode 100644 index 00000000000..7757e5300f3 --- /dev/null +++ b/queue-4.16/media-em28xx-add-hauppauge-solohd-dualhd-bulk-models.patch @@ -0,0 +1,81 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Brad Love +Date: Thu, 4 Jan 2018 19:04:15 -0500 +Subject: media: em28xx: Add Hauppauge SoloHD/DualHD bulk models + +From: Brad Love + +[ Upstream commit f2a326c928cca1f5e36a3dceaf66e8c6b34e9cb8 ] + +Add additional pids to driver list + +Signed-off-by: Brad Love +Reviewed-by: Michael Ira Krufky +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/usb/em28xx/em28xx-cards.c | 22 +++++++++++++++++----- + 1 file changed, 17 insertions(+), 5 deletions(-) + +--- a/drivers/media/usb/em28xx/em28xx-cards.c ++++ b/drivers/media/usb/em28xx/em28xx-cards.c +@@ -507,8 +507,10 @@ static struct em28xx_reg_seq plex_px_bcu + }; + + /* +- * 2040:0265 Hauppauge WinTV-dualHD DVB +- * 2040:026d Hauppauge WinTV-dualHD ATSC/QAM ++ * 2040:0265 Hauppauge WinTV-dualHD DVB Isoc ++ * 2040:8265 Hauppauge WinTV-dualHD DVB Bulk ++ * 2040:026d Hauppauge WinTV-dualHD ATSC/QAM Isoc ++ * 2040:826d Hauppauge WinTV-dualHD ATSC/QAM Bulk + * reg 0x80/0x84: + * GPIO_0: Yellow LED tuner 1, 0=on, 1=off + * GPIO_1: Green LED tuner 1, 0=on, 1=off +@@ -2391,7 +2393,8 @@ struct em28xx_board em28xx_boards[] = { + .has_dvb = 1, + }, + /* +- * 2040:0265 Hauppauge WinTV-dualHD (DVB version). ++ * 2040:0265 Hauppauge WinTV-dualHD (DVB version) Isoc. ++ * 2040:8265 Hauppauge WinTV-dualHD (DVB version) Bulk. + * Empia EM28274, 2x Silicon Labs Si2168, 2x Silicon Labs Si2157 + */ + [EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_DVB] = { +@@ -2406,7 +2409,8 @@ struct em28xx_board em28xx_boards[] = { + .leds = hauppauge_dualhd_leds, + }, + /* +- * 2040:026d Hauppauge WinTV-dualHD (model 01595 - ATSC/QAM). ++ * 2040:026d Hauppauge WinTV-dualHD (model 01595 - ATSC/QAM) Isoc. ++ * 2040:826d Hauppauge WinTV-dualHD (model 01595 - ATSC/QAM) Bulk. + * Empia EM28274, 2x LG LGDT3306A, 2x Silicon Labs Si2157 + */ + [EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_01595] = { +@@ -2547,8 +2551,12 @@ struct usb_device_id em28xx_id_table[] = + .driver_info = EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 }, + { USB_DEVICE(0x2040, 0x0265), + .driver_info = EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_DVB }, ++ { USB_DEVICE(0x2040, 0x8265), ++ .driver_info = EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_DVB }, + { USB_DEVICE(0x2040, 0x026d), + .driver_info = EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_01595 }, ++ { USB_DEVICE(0x2040, 0x826d), ++ .driver_info = EM28174_BOARD_HAUPPAUGE_WINTV_DUALHD_01595 }, + { USB_DEVICE(0x0438, 0xb002), + .driver_info = EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600 }, + { USB_DEVICE(0x2001, 0xf112), +@@ -2609,7 +2617,11 @@ struct usb_device_id em28xx_id_table[] = + .driver_info = EM28178_BOARD_PCTV_461E }, + { USB_DEVICE(0x2013, 0x025f), + .driver_info = EM28178_BOARD_PCTV_292E }, +- { USB_DEVICE(0x2040, 0x0264), /* Hauppauge WinTV-soloHD */ ++ { USB_DEVICE(0x2040, 0x0264), /* Hauppauge WinTV-soloHD Isoc */ ++ .driver_info = EM28178_BOARD_PCTV_292E }, ++ { USB_DEVICE(0x2040, 0x8264), /* Hauppauge OEM Generic WinTV-soloHD Bulk */ ++ .driver_info = EM28178_BOARD_PCTV_292E }, ++ { USB_DEVICE(0x2040, 0x8268), /* Hauppauge Retail WinTV-soloHD Bulk */ + .driver_info = EM28178_BOARD_PCTV_292E }, + { USB_DEVICE(0x0413, 0x6f07), + .driver_info = EM2861_BOARD_LEADTEK_VC100 }, diff --git a/queue-4.16/media-i2c-adv748x-fix-hdmi-field-heights.patch b/queue-4.16/media-i2c-adv748x-fix-hdmi-field-heights.patch new file mode 100644 index 00000000000..407d75cd5b1 --- /dev/null +++ b/queue-4.16/media-i2c-adv748x-fix-hdmi-field-heights.patch @@ -0,0 +1,43 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Kieran Bingham +Date: Mon, 8 Jan 2018 13:14:04 -0500 +Subject: media: i2c: adv748x: fix HDMI field heights + +From: Kieran Bingham + +[ Upstream commit 9f564184e6cc21a86c26bab920afac1bab7653ff ] + +The ADV748x handles interlaced media using V4L2_FIELD_ALTERNATE field +types. The correct specification for the height on the mbus is the +image height, in this instance, the field height. + +The AFE component already correctly adjusts the height on the mbus, but +the HDMI component got left behind. + +Adjust the mbus height to correctly describe the image height of the +fields when processing interlaced video for HDMI pipelines. + +Fixes: 3e89586a64df ("media: i2c: adv748x: add adv748x driver") + +Reviewed-by: Niklas Söderlund +Signed-off-by: Kieran Bingham +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/i2c/adv748x/adv748x-hdmi.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/media/i2c/adv748x/adv748x-hdmi.c ++++ b/drivers/media/i2c/adv748x/adv748x-hdmi.c +@@ -105,6 +105,9 @@ static void adv748x_hdmi_fill_format(str + + fmt->width = hdmi->timings.bt.width; + fmt->height = hdmi->timings.bt.height; ++ ++ if (fmt->field == V4L2_FIELD_ALTERNATE) ++ fmt->height /= 2; + } + + static void adv748x_fill_optional_dv_timings(struct v4l2_dv_timings *timings) diff --git a/queue-4.16/media-lgdt3306a-fix-a-double-kfree-on-i2c-device-remove.patch b/queue-4.16/media-lgdt3306a-fix-a-double-kfree-on-i2c-device-remove.patch new file mode 100644 index 00000000000..10690cad13d --- /dev/null +++ b/queue-4.16/media-lgdt3306a-fix-a-double-kfree-on-i2c-device-remove.patch @@ -0,0 +1,38 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Brad Love +Date: Fri, 5 Jan 2018 09:57:13 -0500 +Subject: media: lgdt3306a: Fix a double kfree on i2c device remove + +From: Brad Love + +[ Upstream commit 94448e21cf08b10f7dc7acdaca387594370396b0 ] + +Both lgdt33606a_release and lgdt3306a_remove kfree state, but _release is +called first, then _remove operates on states members before kfree'ing it. +This can lead to random oops/GPF/etc on USB disconnect. + +Signed-off-by: Brad Love +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/dvb-frontends/lgdt3306a.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/media/dvb-frontends/lgdt3306a.c ++++ b/drivers/media/dvb-frontends/lgdt3306a.c +@@ -1768,7 +1768,13 @@ static void lgdt3306a_release(struct dvb + struct lgdt3306a_state *state = fe->demodulator_priv; + + dbg_info("\n"); +- kfree(state); ++ ++ /* ++ * If state->muxc is not NULL, then we are an i2c device ++ * and lgdt3306a_remove will clean up state ++ */ ++ if (!state->muxc) ++ kfree(state); + } + + static const struct dvb_frontend_ops lgdt3306a_ops; diff --git a/queue-4.16/media-ov5645-add-missing-of_node_put-in-error-path.patch b/queue-4.16/media-ov5645-add-missing-of_node_put-in-error-path.patch new file mode 100644 index 00000000000..1c63b5b5fb8 --- /dev/null +++ b/queue-4.16/media-ov5645-add-missing-of_node_put-in-error-path.patch @@ -0,0 +1,46 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Akinobu Mita +Date: Mon, 19 Mar 2018 12:14:17 -0400 +Subject: media: ov5645: add missing of_node_put() in error path + +From: Akinobu Mita + +[ Upstream commit 06fe932307d58108a11c3e603517dd2a73a57b80 ] + +The device node obtained with of_graph_get_next_endpoint() should be +released by calling of_node_put(). But it was not released when +v4l2_fwnode_endpoint_parse() failed. + +This change moves the of_node_put() call before the error check and +fixes the issue. + +Cc: Mauro Carvalho Chehab +Signed-off-by: Akinobu Mita +Acked-by: Todor Tomov +Signed-off-by: Sakari Ailus +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/i2c/ov5645.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/media/i2c/ov5645.c ++++ b/drivers/media/i2c/ov5645.c +@@ -1131,13 +1131,14 @@ static int ov5645_probe(struct i2c_clien + + ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), + &ov5645->ep); ++ ++ of_node_put(endpoint); ++ + if (ret < 0) { + dev_err(dev, "parsing endpoint node failed\n"); + return ret; + } + +- of_node_put(endpoint); +- + if (ov5645->ep.bus_type != V4L2_MBUS_CSI2) { + dev_err(dev, "invalid bus type, must be CSI2\n"); + return -EINVAL; diff --git a/queue-4.16/media-s3c-camif-fix-out-of-bounds-array-access.patch b/queue-4.16/media-s3c-camif-fix-out-of-bounds-array-access.patch new file mode 100644 index 00000000000..5bd725b74fe --- /dev/null +++ b/queue-4.16/media-s3c-camif-fix-out-of-bounds-array-access.patch @@ -0,0 +1,63 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Arnd Bergmann +Date: Tue, 16 Jan 2018 16:52:15 -0500 +Subject: media: s3c-camif: fix out-of-bounds array access + +From: Arnd Bergmann + +[ Upstream commit a398e043637a4819a0e96467bfecaabf3224dd62 ] + +While experimenting with older compiler versions, I ran +into a warning that no longer shows up on gcc-4.8 or newer: + +drivers/media/platform/s3c-camif/camif-capture.c: In function '__camif_subdev_try_format': +drivers/media/platform/s3c-camif/camif-capture.c:1265:25: error: array subscript is below array bounds + +This is an off-by-one bug, leading to an access before the start of the +array, while newer compilers silently assume this undefined behavior +cannot happen and leave the loop at index 0 if no other entry matches. + +As Sylvester explains, we actually need to ensure that the +value is within the range, so this reworks the loop to be +easier to parse correctly, and an additional check to fall +back on the first format value for any unexpected input. + +I found an existing gcc bug for it and added a reduced version +of the function there. + +Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=69249#c3 +Fixes: babde1c243b2 ("[media] V4L: Add driver for S3C24XX/S3C64XX SoC series camera interface") + +Signed-off-by: Arnd Bergmann +Reviewed-by: Laurent Pinchart +Acked-by: Sakari Ailus +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/platform/s3c-camif/camif-capture.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +--- a/drivers/media/platform/s3c-camif/camif-capture.c ++++ b/drivers/media/platform/s3c-camif/camif-capture.c +@@ -1256,16 +1256,17 @@ static void __camif_subdev_try_format(st + { + const struct s3c_camif_variant *variant = camif->variant; + const struct vp_pix_limits *pix_lim; +- int i = ARRAY_SIZE(camif_mbus_formats); ++ unsigned int i; + + /* FIXME: constraints against codec or preview path ? */ + pix_lim = &variant->vp_pix_limits[VP_CODEC]; + +- while (i-- >= 0) ++ for (i = 0; i < ARRAY_SIZE(camif_mbus_formats); i++) + if (camif_mbus_formats[i] == mf->code) + break; + +- mf->code = camif_mbus_formats[i]; ++ if (i == ARRAY_SIZE(camif_mbus_formats)) ++ mf->code = camif_mbus_formats[0]; + + if (pad == CAMIF_SD_PAD_SINK) { + v4l_bound_align_image(&mf->width, 8, CAMIF_MAX_PIX_WIDTH, diff --git a/queue-4.16/media-v4l-vsp1-fix-display-stalls-when-requesting-too-many-inputs.patch b/queue-4.16/media-v4l-vsp1-fix-display-stalls-when-requesting-too-many-inputs.patch new file mode 100644 index 00000000000..563a6a04f30 --- /dev/null +++ b/queue-4.16/media-v4l-vsp1-fix-display-stalls-when-requesting-too-many-inputs.patch @@ -0,0 +1,41 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Laurent Pinchart +Date: Sun, 3 Dec 2017 05:06:57 -0500 +Subject: media: v4l: vsp1: Fix display stalls when requesting too many inputs + +From: Laurent Pinchart + +[ Upstream commit 5e3e4cb5e24b92773b194aa90066170b12133bc6 ] + +Make sure we don't accept more inputs than the hardware can handle. This +is a temporary fix to avoid display stall, we need to instead allocate +the BRU or BRS to display pipelines dynamically based on the number of +planes they each use. + +Signed-off-by: Laurent Pinchart +Reviewed-by: Kieran Bingham +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/platform/vsp1/vsp1_drm.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/media/platform/vsp1/vsp1_drm.c ++++ b/drivers/media/platform/vsp1/vsp1_drm.c +@@ -530,6 +530,15 @@ void vsp1_du_atomic_flush(struct device + struct vsp1_rwpf *rpf = vsp1->rpf[i]; + unsigned int j; + ++ /* ++ * Make sure we don't accept more inputs than the hardware can ++ * handle. This is a temporary fix to avoid display stall, we ++ * need to instead allocate the BRU or BRS to display pipelines ++ * dynamically based on the number of planes they each use. ++ */ ++ if (pipe->num_inputs >= pipe->bru->source_pad) ++ pipe->inputs[i] = NULL; ++ + if (!pipe->inputs[i]) + continue; + diff --git a/queue-4.16/media-vb2-fix-videobuf2-to-map-correct-area.patch b/queue-4.16/media-vb2-fix-videobuf2-to-map-correct-area.patch new file mode 100644 index 00000000000..33cd7724ae8 --- /dev/null +++ b/queue-4.16/media-vb2-fix-videobuf2-to-map-correct-area.patch @@ -0,0 +1,40 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Masami Hiramatsu +Date: Tue, 6 Feb 2018 03:02:23 -0500 +Subject: media: vb2: Fix videobuf2 to map correct area + +From: Masami Hiramatsu + +[ Upstream commit d13a0139d7874a0577b5955d6eed895517d23b72 ] + +Fixes vb2_vmalloc_get_userptr() to ioremap correct area. +Since the current code does ioremap the page address, if the offset > 0, +it does not do ioremap the last page and results in kernel panic. + +This fixes to pass the size + offset to ioremap so that ioremap +can map correct area. Also, this uses __pfn_to_phys() to get the physical +address of given PFN. + +Signed-off-by: Masami Hiramatsu +Reported-by: Takao Orito +Reported-by: Fumihiro ATSUMI +Reviewed-by: Marek Szyprowski +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/common/videobuf2/videobuf2-vmalloc.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/media/common/videobuf2/videobuf2-vmalloc.c ++++ b/drivers/media/common/videobuf2/videobuf2-vmalloc.c +@@ -106,7 +106,7 @@ static void *vb2_vmalloc_get_userptr(str + if (nums[i-1] + 1 != nums[i]) + goto fail_map; + buf->vaddr = (__force void *) +- ioremap_nocache(nums[0] << PAGE_SHIFT, size); ++ ioremap_nocache(__pfn_to_phys(nums[0]), size + offset); + } else { + buf->vaddr = vm_map_ram(frame_vector_pages(vec), n_pages, -1, + PAGE_KERNEL); diff --git a/queue-4.16/media-vivid-fix-incorrect-capabilities-for-radio.patch b/queue-4.16/media-vivid-fix-incorrect-capabilities-for-radio.patch new file mode 100644 index 00000000000..ef5269145a9 --- /dev/null +++ b/queue-4.16/media-vivid-fix-incorrect-capabilities-for-radio.patch @@ -0,0 +1,42 @@ +From foo@baz Thu May 24 10:36:55 CEST 2018 +From: Hans Verkuil +Date: Thu, 1 Feb 2018 02:36:33 -0500 +Subject: media: vivid: fix incorrect capabilities for radio + +From: Hans Verkuil + +[ Upstream commit 65243386f41d38460bfd4375d231a7c0346d0401 ] + +The vivid driver has two custom controls that change the behavior of RDS. +Depending on the control setting the V4L2_CAP_READWRITE capability is toggled. +However, after an earlier commit the capability was no longer set correctly. +This is now fixed. + +Fixes: 9765a32cd8 ("vivid: set device_caps in video_device") + +Signed-off-by: Hans Verkuil +Signed-off-by: Mauro Carvalho Chehab +Signed-off-by: Sasha Levin +Signed-off-by: Greg Kroah-Hartman +--- + drivers/media/platform/vivid/vivid-ctrls.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/media/platform/vivid/vivid-ctrls.c ++++ b/drivers/media/platform/vivid/vivid-ctrls.c +@@ -1208,6 +1208,7 @@ static int vivid_radio_rx_s_ctrl(struct + v4l2_ctrl_activate(dev->radio_rx_rds_ta, dev->radio_rx_rds_controls); + v4l2_ctrl_activate(dev->radio_rx_rds_tp, dev->radio_rx_rds_controls); + v4l2_ctrl_activate(dev->radio_rx_rds_ms, dev->radio_rx_rds_controls); ++ dev->radio_rx_dev.device_caps = dev->radio_rx_caps; + break; + case V4L2_CID_RDS_RECEPTION: + dev->radio_rx_rds_enabled = ctrl->val; +@@ -1282,6 +1283,7 @@ static int vivid_radio_tx_s_ctrl(struct + dev->radio_tx_caps &= ~V4L2_CAP_READWRITE; + if (!dev->radio_tx_rds_controls) + dev->radio_tx_caps |= V4L2_CAP_READWRITE; ++ dev->radio_tx_dev.device_caps = dev->radio_tx_caps; + break; + case V4L2_CID_RDS_TX_PTY: + if (dev->radio_rx_rds_controls) diff --git a/queue-4.16/series b/queue-4.16/series index 17b804be441..811660e243c 100644 --- a/queue-4.16/series +++ b/queue-4.16/series @@ -114,3 +114,31 @@ scsi-lpfc-fix-nonrecovery-of-nvme-controller-after-cable-swap.patch scsi-lpfc-fix-soft-lockup-in-lpfc-worker-thread-during-lip-testing.patch scsi-lpfc-fix-io-failure-during-hba-reset-testing-with-nvme-io.patch scsi-lpfc-fix-frequency-of-release-wqe-cqes.patch +asoc-rockchip-rk3288-hdmi-analog-select-needed-codecs.patch +asoc-samsung-odroid-fix-32000-sample-rate-handling.patch +asoc-topology-create-tlv-data-for-dapm-widgets.patch +asoc-samsung-i2s-ensure-the-rclk-rate-is-properly-determined.patch +clk-rockchip-fix-wrong-parent-for-sdmmc-phase-clock-for-rk3228.patch +clk-don-t-show-the-incorrect-clock-phase.patch +clk-hisilicon-mark-wdt_mux_p-as-const.patch +clk-tegra-fix-pll_u-rate-configuration.patch +clk-rockchip-prevent-calculating-mmc-phase-if-clock-rate-is-zero.patch +clk-samsung-s3c2410-fix-pll-rates.patch +clk-samsung-exynos7-fix-pll-rates.patch +clk-samsung-exynos5260-fix-pll-rates.patch +clk-samsung-exynos5433-fix-pll-rates.patch +clk-samsung-exynos5250-fix-pll-rates.patch +clk-samsung-exynos3250-fix-pll-rates.patch +clk-meson-axg-fix-the-od-shift-of-the-sys_pll.patch +clk-meson-axg-add-the-fractional-part-of-the-fixed_pll.patch +media-ov5645-add-missing-of_node_put-in-error-path.patch +media-cx23885-override-888-impactvcbe-crystal-frequency.patch +media-cx23885-set-subdev-host-data-to-clk_freq-pointer.patch +media-s3c-camif-fix-out-of-bounds-array-access.patch +media-lgdt3306a-fix-a-double-kfree-on-i2c-device-remove.patch +media-em28xx-add-hauppauge-solohd-dualhd-bulk-models.patch +media-v4l-vsp1-fix-display-stalls-when-requesting-too-many-inputs.patch +media-i2c-adv748x-fix-hdmi-field-heights.patch +media-vb2-fix-videobuf2-to-map-correct-area.patch +media-vivid-fix-incorrect-capabilities-for-radio.patch +media-cx25821-prevent-out-of-bounds-read-on-array-card.patch -- 2.47.2