From 506af0ec815181cc578825af2bdf7c7c5152ebd4 Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Tue, 8 Aug 2023 21:43:30 -0400 Subject: [PATCH] Fixes for 6.4 Signed-off-by: Sasha Levin --- ...sll-fix-wrong-property-name-in-usbph.patch | 36 ++++ ...d-the-gen12_needs_ccs_aux_inv-helper.patch | 88 ++++++++ ...m-i915-gt-add-workaround-14016712196.patch | 111 ++++++++++ ...le-the-ccs_flush-bit-in-the-pipe-con.patch | 79 +++++++ ...re-memory-quiesced-before-invalidati.patch | 47 ++++ ...-aux-invalidation-register-bit-on-in.patch | 87 ++++++++ ...me-flags-with-bit_group_x-according-.patch | 138 ++++++++++++ ...port-aux-invalidation-on-all-engines.patch | 203 ++++++++++++++++++ ...lay-nice-with-binaries-statically-li.patch | 84 ++++++++ queue-6.4/series | 9 + 10 files changed, 882 insertions(+) create mode 100644 queue-6.4/arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch create mode 100644 queue-6.4/drm-i915-add-the-gen12_needs_ccs_aux_inv-helper.patch create mode 100644 queue-6.4/drm-i915-gt-add-workaround-14016712196.patch create mode 100644 queue-6.4/drm-i915-gt-enable-the-ccs_flush-bit-in-the-pipe-con.patch create mode 100644 queue-6.4/drm-i915-gt-ensure-memory-quiesced-before-invalidati.patch create mode 100644 queue-6.4/drm-i915-gt-poll-aux-invalidation-register-bit-on-in.patch create mode 100644 queue-6.4/drm-i915-gt-rename-flags-with-bit_group_x-according-.patch create mode 100644 queue-6.4/drm-i915-gt-support-aux-invalidation-on-all-engines.patch create mode 100644 queue-6.4/selftests-rseq-play-nice-with-binaries-statically-li.patch diff --git a/queue-6.4/arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch b/queue-6.4/arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch new file mode 100644 index 00000000000..eb2432aa437 --- /dev/null +++ b/queue-6.4/arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch @@ -0,0 +1,36 @@ +From c98cca47b4c10e417a30fe78ecaf1d402f84a913 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 17 Jul 2023 10:28:33 +0800 +Subject: ARM: dts: nxp/imx6sll: fix wrong property name in usbphy node + +From: Xu Yang + +[ Upstream commit ee70b908f77a9d8f689dea986f09e6d7dc481934 ] + +Property name "phy-3p0-supply" is used instead of "phy-reg_3p0-supply". + +Fixes: 9f30b6b1a957 ("ARM: dts: imx: Add basic dtsi file for imx6sll") +cc: +Signed-off-by: Xu Yang +Signed-off-by: Shawn Guo +Signed-off-by: Sasha Levin +--- + arch/arm/boot/dts/imx6sll.dtsi | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi +index 2873369a57c02..3659fd5ecfa62 100644 +--- a/arch/arm/boot/dts/imx6sll.dtsi ++++ b/arch/arm/boot/dts/imx6sll.dtsi +@@ -552,7 +552,7 @@ usbphy2: usb-phy@20ca000 { + reg = <0x020ca000 0x1000>; + interrupts = ; + clocks = <&clks IMX6SLL_CLK_USBPHY2>; +- phy-reg_3p0-supply = <®_3p0>; ++ phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + +-- +2.40.1 + diff --git a/queue-6.4/drm-i915-add-the-gen12_needs_ccs_aux_inv-helper.patch b/queue-6.4/drm-i915-add-the-gen12_needs_ccs_aux_inv-helper.patch new file mode 100644 index 00000000000..c1b395faa8f --- /dev/null +++ b/queue-6.4/drm-i915-add-the-gen12_needs_ccs_aux_inv-helper.patch @@ -0,0 +1,88 @@ +From 0a8bb48e6df7a1383498fe8104a2dfc11bf8df6f Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jul 2023 02:19:45 +0200 +Subject: drm/i915: Add the gen12_needs_ccs_aux_inv helper + +From: Andi Shyti + +[ Upstream commit b2f59e9026038a5bbcbc0019fa58f963138211ee ] + +We always assumed that a device might either have AUX or FLAT +CCS, but this is an approximation that is not always true, e.g. +PVC represents an exception. + +Set the basis for future finer selection by implementing a +boolean gen12_needs_ccs_aux_inv() function that tells whether aux +invalidation is needed or not. + +Currently PVC is the only exception to the above mentioned rule. + +Requires: 059ae7ae2a1c ("drm/i915/gt: Cleanup aux invalidation registers") +Signed-off-by: Andi Shyti +Cc: Matt Roper +Cc: Jonathan Cavitt +Cc: # v5.8+ +Reviewed-by: Matt Roper +Reviewed-by: Andrzej Hajda +Reviewed-by: Nirmoy Das +Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-3-andi.shyti@linux.intel.com +(cherry picked from commit c827655b87ad201ebe36f2e28d16b5491c8f7801) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++++++++--- + 1 file changed, 15 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +index f4ed89646fd26..c5b926e3f20d7 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +@@ -165,6 +165,18 @@ static u32 preparser_disable(bool state) + return MI_ARB_CHECK | 1 << 8 | state; + } + ++static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine) ++{ ++ if (IS_PONTEVECCHIO(engine->i915)) ++ return false; ++ ++ /* ++ * so far platforms supported by i915 having ++ * flat ccs do not require AUX invalidation ++ */ ++ return !HAS_FLAT_CCS(engine->i915); ++} ++ + u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg) + { + u32 gsi_offset = gt->uncore->gsi_offset; +@@ -236,7 +248,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + else if (engine->class == COMPUTE_CLASS) + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; + +- if (!HAS_FLAT_CCS(rq->engine->i915)) ++ if (gen12_needs_ccs_aux_inv(rq->engine)) + count = 8 + 4; + else + count = 8; +@@ -254,7 +266,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + + cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); + +- if (!HAS_FLAT_CCS(rq->engine->i915)) { ++ if (gen12_needs_ccs_aux_inv(rq->engine)) { + /* hsdes: 1809175790 */ + cs = gen12_emit_aux_table_inv(rq->engine->gt, cs, + GEN12_CCS_AUX_INV); +@@ -276,7 +288,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) + if (mode & EMIT_INVALIDATE) { + cmd += 2; + +- if (!HAS_FLAT_CCS(rq->engine->i915) && ++ if (gen12_needs_ccs_aux_inv(rq->engine) && + (rq->engine->class == VIDEO_DECODE_CLASS || + rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) { + aux_inv = rq->engine->mask & +-- +2.40.1 + diff --git a/queue-6.4/drm-i915-gt-add-workaround-14016712196.patch b/queue-6.4/drm-i915-gt-add-workaround-14016712196.patch new file mode 100644 index 00000000000..8f078fc1320 --- /dev/null +++ b/queue-6.4/drm-i915-gt-add-workaround-14016712196.patch @@ -0,0 +1,111 @@ +From f202cb3941032f38bb0d0b8c8339ed1e173b93ee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 1 Jun 2023 16:39:59 +0530 +Subject: drm/i915/gt: Add workaround 14016712196 + +From: Tejas Upadhyay + +[ Upstream commit d922b80b1010cd6164fa7d3c197b4fbf94b47beb ] + +For mtl, workaround suggests that, SW insert a +dummy PIPE_CONTROL prior to PIPE_CONTROL which +contains a post sync: Timestamp or Write Immediate. + +Bspec: 72197 + +V5: + - Remove ret variable - Andi +V4: + - Update commit message, avoid returing cs - Andi/Matt +V3: + - Wrap dummy pipe control stuff in API - Andi +V2: + - Fix kernel test robot warnings + +Closes: https://lore.kernel.org/oe-kbuild-all/202305121525.3EWdGoBY-lkp@intel.com/ +Signed-off-by: Tejas Upadhyay +Reviewed-by: Andi Shyti +Reviewed-by: Andrzej Hajda +Signed-off-by: Andi Shyti +Link: https://patchwork.freedesktop.org/patch/msgid/20230601110959.1715927-1-tejas.upadhyay@intel.com +Stable-dep-of: 592b228f12e1 ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet") +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 38 ++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +index 6e914c3f5019a..6210b38a2d382 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +@@ -189,6 +189,27 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv + return cs; + } + ++static int mtl_dummy_pipe_control(struct i915_request *rq) ++{ ++ /* Wa_14016712196 */ ++ if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) || ++ IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) { ++ u32 *cs; ++ ++ /* dummy PIPE_CONTROL + depth flush */ ++ cs = intel_ring_begin(rq, 6); ++ if (IS_ERR(cs)) ++ return PTR_ERR(cs); ++ cs = gen12_emit_pipe_control(cs, ++ 0, ++ PIPE_CONTROL_DEPTH_CACHE_FLUSH, ++ LRC_PPHWSP_SCRATCH_ADDR); ++ intel_ring_advance(rq, cs); ++ } ++ ++ return 0; ++} ++ + int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + { + struct intel_engine_cs *engine = rq->engine; +@@ -199,8 +220,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + */ + if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) { + u32 flags = 0; ++ int err; + u32 *cs; + ++ err = mtl_dummy_pipe_control(rq); ++ if (err) ++ return err; ++ + flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; + flags |= PIPE_CONTROL_FLUSH_L3; + flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; +@@ -233,6 +259,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + if (mode & EMIT_INVALIDATE) { + u32 flags = 0; + u32 *cs, count; ++ int err; ++ ++ err = mtl_dummy_pipe_control(rq); ++ if (err) ++ return err; + + flags |= PIPE_CONTROL_COMMAND_CACHE_INVALIDATE; + flags |= PIPE_CONTROL_TLB_INVALIDATE; +@@ -749,6 +780,13 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) + PIPE_CONTROL_DC_FLUSH_ENABLE | + PIPE_CONTROL_FLUSH_ENABLE); + ++ /* Wa_14016712196 */ ++ if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) || ++ IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) ++ /* dummy PIPE_CONTROL + depth flush */ ++ cs = gen12_emit_pipe_control(cs, 0, ++ PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0); ++ + if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50)) + /* Wa_1409600907 */ + flags |= PIPE_CONTROL_DEPTH_STALL; +-- +2.40.1 + diff --git a/queue-6.4/drm-i915-gt-enable-the-ccs_flush-bit-in-the-pipe-con.patch b/queue-6.4/drm-i915-gt-enable-the-ccs_flush-bit-in-the-pipe-con.patch new file mode 100644 index 00000000000..58af240e712 --- /dev/null +++ b/queue-6.4/drm-i915-gt-enable-the-ccs_flush-bit-in-the-pipe-con.patch @@ -0,0 +1,79 @@ +From 5d7ab7772aeeaa0e9ec872a461ad002160010293 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jul 2023 02:19:48 +0200 +Subject: drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in the + CS + +From: Andi Shyti + +[ Upstream commit 824df77ab2107d8d4740b834b276681a41ae1ac8 ] + +Enable the CCS_FLUSH bit 13 in the control pipe for render and +compute engines in platforms starting from Meteor Lake (BSPEC +43904 and 47112). + +For the copy engine add MI_FLUSH_DW_CCS (bit 16) in the command +streamer. + +Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") +Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet") +Signed-off-by: Andi Shyti +Cc: Jonathan Cavitt +Cc: Nirmoy Das +Cc: # v5.8+ +Reviewed-by: Matt Roper +Reviewed-by: Andrzej Hajda +Reviewed-by: Nirmoy Das +Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-6-andi.shyti@linux.intel.com +(cherry picked from commit b70df82b428774875c7c56d3808102165891547c) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 11 +++++++++++ + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + + 2 files changed, 12 insertions(+) + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +index 024e212b5f80d..2702ad4c26c88 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +@@ -264,6 +264,13 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + + bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; + ++ /* ++ * When required, in MTL and beyond platforms we ++ * need to set the CCS_FLUSH bit in the pipe control ++ */ ++ if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70)) ++ bit_group_0 |= PIPE_CONTROL_CCS_FLUSH; ++ + bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; + bit_group_1 |= PIPE_CONTROL_FLUSH_L3; + bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; +@@ -378,6 +385,10 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) + cmd |= MI_INVALIDATE_TLB; + if (rq->engine->class == VIDEO_DECODE_CLASS) + cmd |= MI_INVALIDATE_BSD; ++ ++ if (gen12_needs_ccs_aux_inv(rq->engine) && ++ rq->engine->class == COPY_ENGINE_CLASS) ++ cmd |= MI_FLUSH_DW_CCS; + } + + *cs++ = cmd; +diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +index 02125a1db2796..2bd8d98d21102 100644 +--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h ++++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +@@ -300,6 +300,7 @@ + #define PIPE_CONTROL_QW_WRITE (1<<14) + #define PIPE_CONTROL_POST_SYNC_OP_MASK (3<<14) + #define PIPE_CONTROL_DEPTH_STALL (1<<13) ++#define PIPE_CONTROL_CCS_FLUSH (1<<13) /* MTL+ */ + #define PIPE_CONTROL_WRITE_FLUSH (1<<12) + #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */ + #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */ +-- +2.40.1 + diff --git a/queue-6.4/drm-i915-gt-ensure-memory-quiesced-before-invalidati.patch b/queue-6.4/drm-i915-gt-ensure-memory-quiesced-before-invalidati.patch new file mode 100644 index 00000000000..e4362153bee --- /dev/null +++ b/queue-6.4/drm-i915-gt-ensure-memory-quiesced-before-invalidati.patch @@ -0,0 +1,47 @@ +From c3bb438b6d84f1553d065ef523bdef61f4d09488 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jul 2023 02:19:46 +0200 +Subject: drm/i915/gt: Ensure memory quiesced before invalidation + +From: Jonathan Cavitt + +[ Upstream commit 78a6ccd65fa3a7cc697810db079cc4b84dff03d5 ] + +All memory traffic must be quiesced before requesting +an aux invalidation on platforms that use Aux CCS. + +Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") +Requires: a2a4aa0eef3b ("drm/i915: Add the gen12_needs_ccs_aux_inv helper") +Signed-off-by: Jonathan Cavitt +Signed-off-by: Andi Shyti +Cc: # v5.8+ +Reviewed-by: Nirmoy Das +Reviewed-by: Andrzej Hajda +Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-4-andi.shyti@linux.intel.com +(cherry picked from commit ad8ebf12217e451cd19804b1c3e97ad56491c74a) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +index c5b926e3f20d7..6e914c3f5019a 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +@@ -193,7 +193,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + { + struct intel_engine_cs *engine = rq->engine; + +- if (mode & EMIT_FLUSH) { ++ /* ++ * On Aux CCS platforms the invalidation of the Aux ++ * table requires quiescing memory traffic beforehand ++ */ ++ if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) { + u32 flags = 0; + u32 *cs; + +-- +2.40.1 + diff --git a/queue-6.4/drm-i915-gt-poll-aux-invalidation-register-bit-on-in.patch b/queue-6.4/drm-i915-gt-poll-aux-invalidation-register-bit-on-in.patch new file mode 100644 index 00000000000..0cf5642b085 --- /dev/null +++ b/queue-6.4/drm-i915-gt-poll-aux-invalidation-register-bit-on-in.patch @@ -0,0 +1,87 @@ +From 5baf9b4f8961e0dffa95e2e519f8dfd1db6263ee Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jul 2023 02:19:49 +0200 +Subject: drm/i915/gt: Poll aux invalidation register bit on invalidation + +From: Jonathan Cavitt + +[ Upstream commit 0fde2f23516a00fd90dfb980b66b4665fcbfa659 ] + +For platforms that use Aux CCS, wait for aux invalidation to +complete by checking the aux invalidation register bit is +cleared. + +Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") +Signed-off-by: Jonathan Cavitt +Signed-off-by: Andi Shyti +Cc: # v5.8+ +Reviewed-by: Nirmoy Das +Reviewed-by: Andrzej Hajda +Reviewed-by: Matt Roper +Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-7-andi.shyti@linux.intel.com +(cherry picked from commit d459c86f00aa98028d155a012c65dc42f7c37e76) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 17 ++++++++++++----- + drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 + + 2 files changed, 13 insertions(+), 5 deletions(-) + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +index 5d2175e918dd2..b2d69ce4a749b 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +@@ -184,7 +184,15 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv + *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN; + *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; + *cs++ = AUX_INV; +- *cs++ = MI_NOOP; ++ ++ *cs++ = MI_SEMAPHORE_WAIT_TOKEN | ++ MI_SEMAPHORE_REGISTER_POLL | ++ MI_SEMAPHORE_POLL | ++ MI_SEMAPHORE_SAD_EQ_SDD; ++ *cs++ = 0; ++ *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; ++ *cs++ = 0; ++ *cs++ = 0; + + return cs; + } +@@ -285,10 +293,9 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + else if (engine->class == COMPUTE_CLASS) + flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; + ++ count = 8; + if (gen12_needs_ccs_aux_inv(rq->engine)) +- count = 8 + 4; +- else +- count = 8; ++ count += 8; + + cs = intel_ring_begin(rq, count); + if (IS_ERR(cs)) +@@ -331,7 +338,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) + aux_inv = rq->engine->mask & + ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0); + if (aux_inv) +- cmd += 4; ++ cmd += 8; + } + } + +diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +index 5d143e2a8db03..02125a1db2796 100644 +--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h ++++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h +@@ -121,6 +121,7 @@ + #define MI_SEMAPHORE_TARGET(engine) ((engine)<<15) + #define MI_SEMAPHORE_WAIT MI_INSTR(0x1c, 2) /* GEN8+ */ + #define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */ ++#define MI_SEMAPHORE_REGISTER_POLL (1 << 16) + #define MI_SEMAPHORE_POLL (1 << 15) + #define MI_SEMAPHORE_SAD_GT_SDD (0 << 12) + #define MI_SEMAPHORE_SAD_GTE_SDD (1 << 12) +-- +2.40.1 + diff --git a/queue-6.4/drm-i915-gt-rename-flags-with-bit_group_x-according-.patch b/queue-6.4/drm-i915-gt-rename-flags-with-bit_group_x-according-.patch new file mode 100644 index 00000000000..96f61d5b335 --- /dev/null +++ b/queue-6.4/drm-i915-gt-rename-flags-with-bit_group_x-according-.patch @@ -0,0 +1,138 @@ +From c2b976a761c1b70aeab69c8a21d279abfb13d840 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jul 2023 02:19:47 +0200 +Subject: drm/i915/gt: Rename flags with bit_group_X according to the datasheet + +From: Andi Shyti + +[ Upstream commit 592b228f12e15867a63e3a6eeeb54c5c12662a62 ] + +In preparation of the next patch align with the datasheet (BSPEC +47112) with the naming of the pipe control set of flag values. +The variable "flags" in gen12_emit_flush_rcs() is applied as a +set of flags called Bit Group 1. + +Define also the Bit Group 0 as bit_group_0 where currently only +PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. + +Signed-off-by: Andi Shyti +Cc: # v5.8+ +Reviewed-by: Matt Roper +Reviewed-by: Andrzej Hajda +Reviewed-by: Nirmoy Das +Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-5-andi.shyti@linux.intel.com +(cherry picked from commit f2dcd21d5a22e13f2fbfe7ab65149038b93cf2ff) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 34 +++++++++++++----------- + drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 18 ++++++++----- + 2 files changed, 29 insertions(+), 23 deletions(-) + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +index 6210b38a2d382..5d2175e918dd2 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +@@ -219,7 +219,8 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + * table requires quiescing memory traffic beforehand + */ + if (mode & EMIT_FLUSH || gen12_needs_ccs_aux_inv(engine)) { +- u32 flags = 0; ++ u32 bit_group_0 = 0; ++ u32 bit_group_1 = 0; + int err; + u32 *cs; + +@@ -227,32 +228,33 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + if (err) + return err; + +- flags |= PIPE_CONTROL_TILE_CACHE_FLUSH; +- flags |= PIPE_CONTROL_FLUSH_L3; +- flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; +- flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; ++ bit_group_0 |= PIPE_CONTROL0_HDC_PIPELINE_FLUSH; ++ ++ bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH; ++ bit_group_1 |= PIPE_CONTROL_FLUSH_L3; ++ bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; ++ bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; + /* Wa_1409600907:tgl,adl-p */ +- flags |= PIPE_CONTROL_DEPTH_STALL; +- flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; +- flags |= PIPE_CONTROL_FLUSH_ENABLE; ++ bit_group_1 |= PIPE_CONTROL_DEPTH_STALL; ++ bit_group_1 |= PIPE_CONTROL_DC_FLUSH_ENABLE; ++ bit_group_1 |= PIPE_CONTROL_FLUSH_ENABLE; + +- flags |= PIPE_CONTROL_STORE_DATA_INDEX; +- flags |= PIPE_CONTROL_QW_WRITE; ++ bit_group_1 |= PIPE_CONTROL_STORE_DATA_INDEX; ++ bit_group_1 |= PIPE_CONTROL_QW_WRITE; + +- flags |= PIPE_CONTROL_CS_STALL; ++ bit_group_1 |= PIPE_CONTROL_CS_STALL; + + if (!HAS_3D_PIPELINE(engine->i915)) +- flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; ++ bit_group_1 &= ~PIPE_CONTROL_3D_ARCH_FLAGS; + else if (engine->class == COMPUTE_CLASS) +- flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; ++ bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; + + cs = intel_ring_begin(rq, 6); + if (IS_ERR(cs)) + return PTR_ERR(cs); + +- cs = gen12_emit_pipe_control(cs, +- PIPE_CONTROL0_HDC_PIPELINE_FLUSH, +- flags, LRC_PPHWSP_SCRATCH_ADDR); ++ cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1, ++ LRC_PPHWSP_SCRATCH_ADDR); + intel_ring_advance(rq, cs); + } + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h +index 655e5c00ddc27..a44eda096557c 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h +@@ -49,25 +49,29 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); + u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg); + + static inline u32 * +-__gen8_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) ++__gen8_emit_pipe_control(u32 *batch, u32 bit_group_0, ++ u32 bit_group_1, u32 offset) + { + memset(batch, 0, 6 * sizeof(u32)); + +- batch[0] = GFX_OP_PIPE_CONTROL(6) | flags0; +- batch[1] = flags1; ++ batch[0] = GFX_OP_PIPE_CONTROL(6) | bit_group_0; ++ batch[1] = bit_group_1; + batch[2] = offset; + + return batch + 6; + } + +-static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) ++static inline u32 *gen8_emit_pipe_control(u32 *batch, ++ u32 bit_group_1, u32 offset) + { +- return __gen8_emit_pipe_control(batch, 0, flags, offset); ++ return __gen8_emit_pipe_control(batch, 0, bit_group_1, offset); + } + +-static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 flags0, u32 flags1, u32 offset) ++static inline u32 *gen12_emit_pipe_control(u32 *batch, u32 bit_group_0, ++ u32 bit_group_1, u32 offset) + { +- return __gen8_emit_pipe_control(batch, flags0, flags1, offset); ++ return __gen8_emit_pipe_control(batch, bit_group_0, ++ bit_group_1, offset); + } + + static inline u32 * +-- +2.40.1 + diff --git a/queue-6.4/drm-i915-gt-support-aux-invalidation-on-all-engines.patch b/queue-6.4/drm-i915-gt-support-aux-invalidation-on-all-engines.patch new file mode 100644 index 00000000000..11022f71512 --- /dev/null +++ b/queue-6.4/drm-i915-gt-support-aux-invalidation-on-all-engines.patch @@ -0,0 +1,203 @@ +From 24d1b866d1945126b155d45a0dfce4c92b4c4bf5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 25 Jul 2023 02:19:50 +0200 +Subject: drm/i915/gt: Support aux invalidation on all engines + +From: Andi Shyti + +[ Upstream commit 6a35f22d222528e1b157c6978c9424d2f8cbe0a1 ] + +Perform some refactoring with the purpose of keeping in one +single place all the operations around the aux table +invalidation. + +With this refactoring add more engines where the invalidation +should be performed. + +Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") +Signed-off-by: Andi Shyti +Cc: Jonathan Cavitt +Cc: Matt Roper +Cc: # v5.8+ +Reviewed-by: Andrzej Hajda +Link: https://patchwork.freedesktop.org/patch/msgid/20230725001950.1014671-8-andi.shyti@linux.intel.com +(cherry picked from commit 76ff7789d6e63d1a10b3b58f5c70b2e640c7a880) +Signed-off-by: Tvrtko Ursulin +Signed-off-by: Sasha Levin +--- + drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 66 +++++++++++++----------- + drivers/gpu/drm/i915/gt/gen8_engine_cs.h | 3 +- + drivers/gpu/drm/i915/gt/intel_lrc.c | 17 +----- + 3 files changed, 41 insertions(+), 45 deletions(-) + +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +index b2d69ce4a749b..024e212b5f80d 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c +@@ -165,21 +165,47 @@ static u32 preparser_disable(bool state) + return MI_ARB_CHECK | 1 << 8 | state; + } + ++static i915_reg_t gen12_get_aux_inv_reg(struct intel_engine_cs *engine) ++{ ++ switch (engine->id) { ++ case RCS0: ++ return GEN12_CCS_AUX_INV; ++ case BCS0: ++ return GEN12_BCS0_AUX_INV; ++ case VCS0: ++ return GEN12_VD0_AUX_INV; ++ case VCS2: ++ return GEN12_VD2_AUX_INV; ++ case VECS0: ++ return GEN12_VE0_AUX_INV; ++ case CCS0: ++ return GEN12_CCS0_AUX_INV; ++ default: ++ return INVALID_MMIO_REG; ++ } ++} ++ + static bool gen12_needs_ccs_aux_inv(struct intel_engine_cs *engine) + { ++ i915_reg_t reg = gen12_get_aux_inv_reg(engine); ++ + if (IS_PONTEVECCHIO(engine->i915)) + return false; + + /* +- * so far platforms supported by i915 having +- * flat ccs do not require AUX invalidation ++ * So far platforms supported by i915 having flat ccs do not require ++ * AUX invalidation. Check also whether the engine requires it. + */ +- return !HAS_FLAT_CCS(engine->i915); ++ return i915_mmio_reg_valid(reg) && !HAS_FLAT_CCS(engine->i915); + } + +-u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg) ++u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs) + { +- u32 gsi_offset = gt->uncore->gsi_offset; ++ i915_reg_t inv_reg = gen12_get_aux_inv_reg(engine); ++ u32 gsi_offset = engine->gt->uncore->gsi_offset; ++ ++ if (!gen12_needs_ccs_aux_inv(engine)) ++ return cs; + + *cs++ = MI_LOAD_REGISTER_IMM(1) | MI_LRI_MMIO_REMAP_EN; + *cs++ = i915_mmio_reg_offset(inv_reg) + gsi_offset; +@@ -310,11 +336,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + + cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR); + +- if (gen12_needs_ccs_aux_inv(rq->engine)) { +- /* hsdes: 1809175790 */ +- cs = gen12_emit_aux_table_inv(rq->engine->gt, cs, +- GEN12_CCS_AUX_INV); +- } ++ cs = gen12_emit_aux_table_inv(engine, cs); + + *cs++ = preparser_disable(false); + intel_ring_advance(rq, cs); +@@ -325,21 +347,14 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode) + + int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) + { +- intel_engine_mask_t aux_inv = 0; +- u32 cmd, *cs; ++ u32 cmd = 4; ++ u32 *cs; + +- cmd = 4; + if (mode & EMIT_INVALIDATE) { + cmd += 2; + +- if (gen12_needs_ccs_aux_inv(rq->engine) && +- (rq->engine->class == VIDEO_DECODE_CLASS || +- rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) { +- aux_inv = rq->engine->mask & +- ~GENMASK(_BCS(I915_MAX_BCS - 1), BCS0); +- if (aux_inv) +- cmd += 8; +- } ++ if (gen12_needs_ccs_aux_inv(rq->engine)) ++ cmd += 8; + } + + cs = intel_ring_begin(rq, cmd); +@@ -370,14 +385,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode) + *cs++ = 0; /* upper addr */ + *cs++ = 0; /* value */ + +- if (aux_inv) { /* hsdes: 1809175790 */ +- if (rq->engine->class == VIDEO_DECODE_CLASS) +- cs = gen12_emit_aux_table_inv(rq->engine->gt, +- cs, GEN12_VD0_AUX_INV); +- else +- cs = gen12_emit_aux_table_inv(rq->engine->gt, +- cs, GEN12_VE0_AUX_INV); +- } ++ cs = gen12_emit_aux_table_inv(rq->engine, cs); + + if (mode & EMIT_INVALIDATE) + *cs++ = preparser_disable(false); +diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h +index a44eda096557c..867ba697aceb8 100644 +--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.h ++++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.h +@@ -13,6 +13,7 @@ + #include "intel_gt_regs.h" + #include "intel_gpu_commands.h" + ++struct intel_engine_cs; + struct intel_gt; + struct i915_request; + +@@ -46,7 +47,7 @@ u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); + u32 *gen11_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); + u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs); + +-u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv_reg); ++u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs); + + static inline u32 * + __gen8_emit_pipe_control(u32 *batch, u32 bit_group_0, +diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c +index c0c16c06eb29e..502a1c0093aab 100644 +--- a/drivers/gpu/drm/i915/gt/intel_lrc.c ++++ b/drivers/gpu/drm/i915/gt/intel_lrc.c +@@ -1364,10 +1364,7 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) + IS_DG2_G11(ce->engine->i915)) + cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); + +- /* hsdes: 1809175790 */ +- if (!HAS_FLAT_CCS(ce->engine->i915)) +- cs = gen12_emit_aux_table_inv(ce->engine->gt, +- cs, GEN12_CCS_AUX_INV); ++ cs = gen12_emit_aux_table_inv(ce->engine, cs); + + /* Wa_16014892111 */ + if (IS_DG2(ce->engine->i915)) +@@ -1390,17 +1387,7 @@ gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs) + PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, + 0); + +- /* hsdes: 1809175790 */ +- if (!HAS_FLAT_CCS(ce->engine->i915)) { +- if (ce->engine->class == VIDEO_DECODE_CLASS) +- cs = gen12_emit_aux_table_inv(ce->engine->gt, +- cs, GEN12_VD0_AUX_INV); +- else if (ce->engine->class == VIDEO_ENHANCEMENT_CLASS) +- cs = gen12_emit_aux_table_inv(ce->engine->gt, +- cs, GEN12_VE0_AUX_INV); +- } +- +- return cs; ++ return gen12_emit_aux_table_inv(ce->engine, cs); + } + + static void +-- +2.40.1 + diff --git a/queue-6.4/selftests-rseq-play-nice-with-binaries-statically-li.patch b/queue-6.4/selftests-rseq-play-nice-with-binaries-statically-li.patch new file mode 100644 index 00000000000..07422257015 --- /dev/null +++ b/queue-6.4/selftests-rseq-play-nice-with-binaries-statically-li.patch @@ -0,0 +1,84 @@ +From 2fdc485f16bfc9f86ee98a02a9157940444d1925 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Fri, 21 Jul 2023 15:33:52 -0700 +Subject: selftests/rseq: Play nice with binaries statically linked against + glibc 2.35+ + +From: Sean Christopherson + +[ Upstream commit 3bcbc20942db5d738221cca31a928efc09827069 ] + +To allow running rseq and KVM's rseq selftests as statically linked +binaries, initialize the various "trampoline" pointers to point directly +at the expect glibc symbols, and skip the dlysm() lookups if the rseq +size is non-zero, i.e. the binary is statically linked *and* the libc +registered its own rseq. + +Define weak versions of the symbols so as not to break linking against +libc versions that don't support rseq in any capacity. + +The KVM selftests in particular are often statically linked so that they +can be run on targets with very limited runtime environments, i.e. test +machines. + +Fixes: 233e667e1ae3 ("selftests/rseq: Uplift rseq selftests for compatibility with glibc-2.35") +Cc: Aaron Lewis +Cc: kvm@vger.kernel.org +Cc: stable@vger.kernel.org +Signed-off-by: Sean Christopherson +Message-Id: <20230721223352.2333911-1-seanjc@google.com> +Signed-off-by: Paolo Bonzini +Signed-off-by: Sasha Levin +--- + tools/testing/selftests/rseq/rseq.c | 28 ++++++++++++++++++++++------ + 1 file changed, 22 insertions(+), 6 deletions(-) + +diff --git a/tools/testing/selftests/rseq/rseq.c b/tools/testing/selftests/rseq/rseq.c +index 4e4aa006004c8..a723da2532441 100644 +--- a/tools/testing/selftests/rseq/rseq.c ++++ b/tools/testing/selftests/rseq/rseq.c +@@ -34,9 +34,17 @@ + #include "../kselftest.h" + #include "rseq.h" + +-static const ptrdiff_t *libc_rseq_offset_p; +-static const unsigned int *libc_rseq_size_p; +-static const unsigned int *libc_rseq_flags_p; ++/* ++ * Define weak versions to play nice with binaries that are statically linked ++ * against a libc that doesn't support registering its own rseq. ++ */ ++__weak ptrdiff_t __rseq_offset; ++__weak unsigned int __rseq_size; ++__weak unsigned int __rseq_flags; ++ ++static const ptrdiff_t *libc_rseq_offset_p = &__rseq_offset; ++static const unsigned int *libc_rseq_size_p = &__rseq_size; ++static const unsigned int *libc_rseq_flags_p = &__rseq_flags; + + /* Offset from the thread pointer to the rseq area. */ + ptrdiff_t rseq_offset; +@@ -155,9 +163,17 @@ unsigned int get_rseq_feature_size(void) + static __attribute__((constructor)) + void rseq_init(void) + { +- libc_rseq_offset_p = dlsym(RTLD_NEXT, "__rseq_offset"); +- libc_rseq_size_p = dlsym(RTLD_NEXT, "__rseq_size"); +- libc_rseq_flags_p = dlsym(RTLD_NEXT, "__rseq_flags"); ++ /* ++ * If the libc's registered rseq size isn't already valid, it may be ++ * because the binary is dynamically linked and not necessarily due to ++ * libc not having registered a restartable sequence. Try to find the ++ * symbols if that's the case. ++ */ ++ if (!*libc_rseq_size_p) { ++ libc_rseq_offset_p = dlsym(RTLD_NEXT, "__rseq_offset"); ++ libc_rseq_size_p = dlsym(RTLD_NEXT, "__rseq_size"); ++ libc_rseq_flags_p = dlsym(RTLD_NEXT, "__rseq_flags"); ++ } + if (libc_rseq_size_p && libc_rseq_offset_p && libc_rseq_flags_p && + *libc_rseq_size_p != 0) { + /* rseq registration owned by glibc */ +-- +2.40.1 + diff --git a/queue-6.4/series b/queue-6.4/series index f8e84f9f866..2dd9be77a1c 100644 --- a/queue-6.4/series +++ b/queue-6.4/series @@ -154,3 +154,12 @@ mtd-rawnand-fsl_upm-fix-an-off-by-one-test-in-fun_ex.patch powerpc-mm-altmap-fix-altmap-boundary-check.patch drm-imx-ipuv3-fix-front-porch-adjustment-upon-hactiv.patch drm-amdgpu-use-apt-name-for-fw-reserved-region.patch +selftests-rseq-play-nice-with-binaries-statically-li.patch +arm-dts-nxp-imx6sll-fix-wrong-property-name-in-usbph.patch +drm-i915-add-the-gen12_needs_ccs_aux_inv-helper.patch +drm-i915-gt-ensure-memory-quiesced-before-invalidati.patch +drm-i915-gt-add-workaround-14016712196.patch +drm-i915-gt-rename-flags-with-bit_group_x-according-.patch +drm-i915-gt-poll-aux-invalidation-register-bit-on-in.patch +drm-i915-gt-support-aux-invalidation-on-all-engines.patch +drm-i915-gt-enable-the-ccs_flush-bit-in-the-pipe-con.patch -- 2.47.3