From 51cde9bcf3b4039daf955074a0c000c668aa1f8b Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 18 Dec 2013 13:00:31 -0800 Subject: [PATCH] 3.12-stable patches added patches: drm-i915-vlv-add-vlv-specific-clock_get-function-v3.patch drm-i915-vlv-fix-up-broken-precision-in-vlv_crtc_clock_get.patch i915-vlv-untangle-integrated-clock-source-handling-v4.patch --- ...d-vlv-specific-clock_get-function-v3.patch | 73 ++++++++++++ ...oken-precision-in-vlv_crtc_clock_get.patch | 47 ++++++++ ...-integrated-clock-source-handling-v4.patch | 106 ++++++++++++++++++ queue-3.12/series | 3 + 4 files changed, 229 insertions(+) create mode 100644 queue-3.12/drm-i915-vlv-add-vlv-specific-clock_get-function-v3.patch create mode 100644 queue-3.12/drm-i915-vlv-fix-up-broken-precision-in-vlv_crtc_clock_get.patch create mode 100644 queue-3.12/i915-vlv-untangle-integrated-clock-source-handling-v4.patch diff --git a/queue-3.12/drm-i915-vlv-add-vlv-specific-clock_get-function-v3.patch b/queue-3.12/drm-i915-vlv-add-vlv-specific-clock_get-function-v3.patch new file mode 100644 index 00000000000..ecac2ae29cd --- /dev/null +++ b/queue-3.12/drm-i915-vlv-add-vlv-specific-clock_get-function-v3.patch @@ -0,0 +1,73 @@ +From acbec814a27f233b5ddb88a1bcaa2ac20daf64e0 Mon Sep 17 00:00:00 2001 +From: Jesse Barnes +Date: Fri, 20 Sep 2013 11:29:32 -0700 +Subject: drm/i915/vlv: add VLV specific clock_get function v3 + +From: Jesse Barnes + +commit acbec814a27f233b5ddb88a1bcaa2ac20daf64e0 upstream. + +Calculation is a little different than other platforms. + +v2: update to use port_clock instead + rebase on top of Ville's changes +v3: update to new port_clock semantics - don't divide by + pixel_multiplier (Ville) + +References: https://bugs.freedesktop.org/show_bug.cgi?id=67345 +Signed-off-by: Jesse Barnes +Reviewed-by: Ville Syrjälä +Signed-off-by: Daniel Vetter +Signed-off-by: Ville Syrjälä +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++++++++- + 1 file changed, 29 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -5032,6 +5032,34 @@ static void i9xx_get_pfit_config(struct + I915_READ(LVDS) & LVDS_BORDER_ENABLE; + } + ++static void vlv_crtc_clock_get(struct intel_crtc *crtc, ++ struct intel_crtc_config *pipe_config) ++{ ++ struct drm_device *dev = crtc->base.dev; ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ int pipe = pipe_config->cpu_transcoder; ++ intel_clock_t clock; ++ u32 mdiv; ++ int refclk = 100000, fastclk, update_rate; ++ ++ mutex_lock(&dev_priv->dpio_lock); ++ mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); ++ mutex_unlock(&dev_priv->dpio_lock); ++ ++ clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; ++ clock.m2 = mdiv & DPIO_M2DIV_MASK; ++ clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; ++ clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; ++ clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; ++ ++ update_rate = refclk / clock.n; ++ clock.vco = update_rate * clock.m1 * clock.m2; ++ fastclk = clock.vco / clock.p1 / clock.p2; ++ clock.dot = (2 * fastclk); ++ ++ pipe_config->adjusted_mode.clock = clock.dot / 10; ++} ++ + static bool i9xx_get_pipe_config(struct intel_crtc *crtc, + struct intel_crtc_config *pipe_config) + { +@@ -9849,7 +9877,7 @@ static void intel_init_display(struct dr + dev_priv->display.update_plane = ironlake_update_plane; + } else if (IS_VALLEYVIEW(dev)) { + dev_priv->display.get_pipe_config = i9xx_get_pipe_config; +- dev_priv->display.get_clock = i9xx_crtc_clock_get; ++ dev_priv->display.get_clock = vlv_crtc_clock_get; + dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; + dev_priv->display.crtc_enable = valleyview_crtc_enable; + dev_priv->display.crtc_disable = i9xx_crtc_disable; diff --git a/queue-3.12/drm-i915-vlv-fix-up-broken-precision-in-vlv_crtc_clock_get.patch b/queue-3.12/drm-i915-vlv-fix-up-broken-precision-in-vlv_crtc_clock_get.patch new file mode 100644 index 00000000000..36a55f56684 --- /dev/null +++ b/queue-3.12/drm-i915-vlv-fix-up-broken-precision-in-vlv_crtc_clock_get.patch @@ -0,0 +1,47 @@ +From 662c6ecbcdca1fe8a5402f6c83d98d242917a043 Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Wed, 25 Sep 2013 14:24:01 -0700 +Subject: drm/i915/vlv: fix up broken precision in vlv_crtc_clock_get + +From: Chris Wilson + +commit 662c6ecbcdca1fe8a5402f6c83d98d242917a043 upstream. + +With some divider values we end up with the wrong result. So remove the +intermediates (like Ville suggested in the first place) to get the right +answer. + +Signed-off-by: Chris Wilson +Signed-off-by: Jesse Barnes +Signed-off-by: Daniel Vetter +Signed-off-by: Ville Syrjälä +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -5040,7 +5040,7 @@ static void vlv_crtc_clock_get(struct in + int pipe = pipe_config->cpu_transcoder; + intel_clock_t clock; + u32 mdiv; +- int refclk = 100000, fastclk, update_rate; ++ int refclk = 100000; + + mutex_lock(&dev_priv->dpio_lock); + mdiv = vlv_dpio_read(dev_priv, DPIO_DIV(pipe)); +@@ -5052,10 +5052,8 @@ static void vlv_crtc_clock_get(struct in + clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; + clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; + +- update_rate = refclk / clock.n; +- clock.vco = update_rate * clock.m1 * clock.m2; +- fastclk = clock.vco / clock.p1 / clock.p2; +- clock.dot = (2 * fastclk); ++ clock.vco = refclk * clock.m1 * clock.m2 / clock.n; ++ clock.dot = 2 * clock.vco / (clock.p1 * clock.p2); + + pipe_config->adjusted_mode.clock = clock.dot / 10; + } diff --git a/queue-3.12/i915-vlv-untangle-integrated-clock-source-handling-v4.patch b/queue-3.12/i915-vlv-untangle-integrated-clock-source-handling-v4.patch new file mode 100644 index 00000000000..455db7c8fc8 --- /dev/null +++ b/queue-3.12/i915-vlv-untangle-integrated-clock-source-handling-v4.patch @@ -0,0 +1,106 @@ +From f60711666bcab6df2c6c91d851e07ed54088453c Mon Sep 17 00:00:00 2001 +From: Jesse Barnes +Date: Tue, 1 Oct 2013 10:41:38 -0700 +Subject: i915/vlv: untangle integrated clock source handling v4 + +From: Jesse Barnes + +commit f60711666bcab6df2c6c91d851e07ed54088453c upstream. + +The global integrated clock source bit resides in DPLL B on VLV, but we +were treating it as a per-pipe resource. It needs to be set whenever +any PLL is active, so pull setting the bit out of vlv_update_pll and +into vlv_enable_pll. Also add a vlv_disable_pll to prevent disabling it +when pipe B shuts down. + +I'm guessing on the references here, I expect this to bite any config +where multiple displays are active or displays are moved from pipe to +pipe. + +v2: re-add bits in vlv_update_pll to keep from confusing the state checker +v3: use enum pipe checks (Daniel) + set CRI clock source early (Ville) + consistently set CRI clock source everywhere (Ville) +v4: drop unnecessary setting of bit in vlv enable pll (Ville) + +References: https://bugs.freedesktop.org/show_bug.cgi?id=67245 +References: https://bugs.freedesktop.org/show_bug.cgi?id=69693 +Signed-off-by: Jesse Barnes +Reviewed-by: Ville Syrjälä +[danvet: s/1/PIPE_B/] +Signed-off-by: Daniel Vetter +Signed-off-by: Ville Syrjälä +Signed-off-by: Greg Kroah-Hartman + + +--- + drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++++++--- + 1 file changed, 27 insertions(+), 3 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -1429,6 +1429,20 @@ static void i9xx_disable_pll(struct drm_ + POSTING_READ(DPLL(pipe)); + } + ++static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) ++{ ++ u32 val = 0; ++ ++ /* Make sure the pipe isn't still relying on us */ ++ assert_pipe_disabled(dev_priv, pipe); ++ ++ /* Leave integrated clock source enabled */ ++ if (pipe == PIPE_B) ++ val = DPLL_INTEGRATED_CRI_CLK_VLV; ++ I915_WRITE(DPLL(pipe), val); ++ POSTING_READ(DPLL(pipe)); ++} ++ + void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) + { + u32 port_mask; +@@ -3824,7 +3838,10 @@ static void i9xx_crtc_disable(struct drm + if (encoder->post_disable) + encoder->post_disable(encoder); + +- i9xx_disable_pll(dev_priv, pipe); ++ if (IS_VALLEYVIEW(dev)) ++ vlv_disable_pll(dev_priv, pipe); ++ else ++ i9xx_disable_pll(dev_priv, pipe); + + intel_crtc->active = false; + intel_update_fbc(dev); +@@ -4553,9 +4570,9 @@ static void vlv_update_pll(struct intel_ + /* Enable DPIO clock input */ + dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | + DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; +- if (pipe) ++ /* We should never disable this, set it here for state tracking */ ++ if (pipe == PIPE_B) + dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; +- + dpll |= DPLL_VCO_ENABLE; + crtc->config.dpll_hw_state.dpll = dpll; + +@@ -10088,12 +10105,19 @@ static void i915_disable_vga(struct drm_ + + void intel_modeset_init_hw(struct drm_device *dev) + { ++ struct drm_i915_private *dev_priv = dev->dev_private; ++ + intel_init_power_well(dev); + + intel_prepare_ddi(dev); + + intel_init_clock_gating(dev); + ++ /* Enable the CRI clock source so we can get at the display */ ++ if (IS_VALLEYVIEW(dev)) ++ I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | ++ DPLL_INTEGRATED_CRI_CLK_VLV); ++ + mutex_lock(&dev->struct_mutex); + intel_enable_gt_powersave(dev); + mutex_unlock(&dev->struct_mutex); diff --git a/queue-3.12/series b/queue-3.12/series index c2db0092adf..0ac82fc3308 100644 --- a/queue-3.12/series +++ b/queue-3.12/series @@ -113,3 +113,6 @@ btrfs-take-ordered-root-lock-when-removing-ordered-operations-inode.patch btrfs-do-not-run-snapshot-aware-defragment-on-error.patch btrfs-fix-a-crash-when-running-balance-and-defrag-concurrently.patch btrfs-fix-lockdep-error-in-async-commit.patch +i915-vlv-untangle-integrated-clock-source-handling-v4.patch +drm-i915-vlv-add-vlv-specific-clock_get-function-v3.patch +drm-i915-vlv-fix-up-broken-precision-in-vlv_crtc_clock_get.patch -- 2.47.3