From 53f8de00b2afa7ae172a6093901e9184adbe5ea2 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 23 Dec 2019 12:35:15 -0500 Subject: [PATCH] 4.14-stable patches added patches: mmc-mediatek-fix-cmd_ta-to-2-for-mt8173-hs200-hs400-mode.patch revert-mmc-sdhci-fix-incorrect-switch-to-hs-mode.patch --- ..._ta-to-2-for-mt8173-hs200-hs400-mode.patch | 44 +++++++++++++++++++ ...dhci-fix-incorrect-switch-to-hs-mode.patch | 42 ++++++++++++++++++ queue-4.14/series | 2 + 3 files changed, 88 insertions(+) create mode 100644 queue-4.14/mmc-mediatek-fix-cmd_ta-to-2-for-mt8173-hs200-hs400-mode.patch create mode 100644 queue-4.14/revert-mmc-sdhci-fix-incorrect-switch-to-hs-mode.patch diff --git a/queue-4.14/mmc-mediatek-fix-cmd_ta-to-2-for-mt8173-hs200-hs400-mode.patch b/queue-4.14/mmc-mediatek-fix-cmd_ta-to-2-for-mt8173-hs200-hs400-mode.patch new file mode 100644 index 00000000000..39dea46e3d4 --- /dev/null +++ b/queue-4.14/mmc-mediatek-fix-cmd_ta-to-2-for-mt8173-hs200-hs400-mode.patch @@ -0,0 +1,44 @@ +From 8f34e5bd7024d1ffebddd82d7318b1be17be9e9a Mon Sep 17 00:00:00 2001 +From: Chaotian Jing +Date: Wed, 4 Dec 2019 15:19:58 +0800 +Subject: mmc: mediatek: fix CMD_TA to 2 for MT8173 HS200/HS400 mode + +From: Chaotian Jing + +commit 8f34e5bd7024d1ffebddd82d7318b1be17be9e9a upstream. + +there is a chance that always get response CRC error after HS200 tuning, +the reason is that need set CMD_TA to 2. this modification is only for +MT8173. + +Signed-off-by: Chaotian Jing +Tested-by: Hsin-Yi Wang +Cc: stable@vger.kernel.org +Fixes: 1ede5cb88a29 ("mmc: mediatek: Use data tune for CMD line tune") +Link: https://lore.kernel.org/r/20191204071958.18553-1-chaotian.jing@mediatek.com +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mmc/host/mtk-sd.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/mmc/host/mtk-sd.c ++++ b/drivers/mmc/host/mtk-sd.c +@@ -212,6 +212,8 @@ + #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ + #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ + ++#define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ ++ + #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ + #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ + #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ +@@ -1442,6 +1444,7 @@ static int hs400_tune_response(struct mm + + /* select EMMC50 PAD CMD tune */ + sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); ++ sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); + + if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || + mmc->ios.timing == MMC_TIMING_UHS_SDR104) diff --git a/queue-4.14/revert-mmc-sdhci-fix-incorrect-switch-to-hs-mode.patch b/queue-4.14/revert-mmc-sdhci-fix-incorrect-switch-to-hs-mode.patch new file mode 100644 index 00000000000..7d86c1dc268 --- /dev/null +++ b/queue-4.14/revert-mmc-sdhci-fix-incorrect-switch-to-hs-mode.patch @@ -0,0 +1,42 @@ +From 07bcc411567cb96f9d1fc84fff8d387118a2920d Mon Sep 17 00:00:00 2001 +From: Faiz Abbas +Date: Thu, 28 Nov 2019 16:34:22 +0530 +Subject: Revert "mmc: sdhci: Fix incorrect switch to HS mode" + +From: Faiz Abbas + +commit 07bcc411567cb96f9d1fc84fff8d387118a2920d upstream. + +This reverts commit c894e33ddc1910e14d6f2a2016f60ab613fd8b37. + +This commit aims to treat SD High speed and SDR25 as the same while +setting UHS Timings in HOST_CONTROL2 which leads to failures with some +SD cards in AM65x. Revert this commit. + +The issue this commit was trying to fix can be implemented in a platform +specific callback instead of common sdhci code. + +Cc: +Signed-off-by: Faiz Abbas +Acked-by: Adrian Hunter +Link: https://lore.kernel.org/r/20191128110422.25917-1-faiz_abbas@ti.com +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mmc/host/sdhci.c | 4 +--- + 1 file changed, 1 insertion(+), 3 deletions(-) + +--- a/drivers/mmc/host/sdhci.c ++++ b/drivers/mmc/host/sdhci.c +@@ -1635,9 +1635,7 @@ void sdhci_set_uhs_signaling(struct sdhc + ctrl_2 |= SDHCI_CTRL_UHS_SDR104; + else if (timing == MMC_TIMING_UHS_SDR12) + ctrl_2 |= SDHCI_CTRL_UHS_SDR12; +- else if (timing == MMC_TIMING_SD_HS || +- timing == MMC_TIMING_MMC_HS || +- timing == MMC_TIMING_UHS_SDR25) ++ else if (timing == MMC_TIMING_UHS_SDR25) + ctrl_2 |= SDHCI_CTRL_UHS_SDR25; + else if (timing == MMC_TIMING_UHS_SDR50) + ctrl_2 |= SDHCI_CTRL_UHS_SDR50; diff --git a/queue-4.14/series b/queue-4.14/series index 065ae8f1943..84609e3236c 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -128,3 +128,5 @@ perf-intel-bts-does-not-support-aux-area-sampling.patch net-phy-initialise-phydev-speed-and-duplex-sanely.patch btrfs-don-t-prematurely-free-work-in-reada_start_mac.patch btrfs-don-t-prematurely-free-work-in-scrub_missing_r.patch +revert-mmc-sdhci-fix-incorrect-switch-to-hs-mode.patch +mmc-mediatek-fix-cmd_ta-to-2-for-mt8173-hs200-hs400-mode.patch -- 2.47.3