From 56cd5a68c7e17312ca3b53748948f1fa1ba43b40 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 15 Mar 2023 12:38:47 +0100 Subject: [PATCH] 4.14-stable patches added patches: x86-cpu-fix-lfence-serialization-check-in-init_amd.patch --- queue-4.14/series | 1 + ...ence-serialization-check-in-init_amd.patch | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 queue-4.14/x86-cpu-fix-lfence-serialization-check-in-init_amd.patch diff --git a/queue-4.14/series b/queue-4.14/series index ad773c3d24a..44ff4d17356 100644 --- a/queue-4.14/series +++ b/queue-4.14/series @@ -18,3 +18,4 @@ pci-avoid-flr-for-solidrun-snet-dpu-rev-1.patch media-ov5640-fix-analogue-gain-control.patch tipc-improve-function-tipc_wait_for_cond.patch drm-i915-don-t-use-bar-mappings-for-ring-buffers-with-llc.patch +x86-cpu-fix-lfence-serialization-check-in-init_amd.patch diff --git a/queue-4.14/x86-cpu-fix-lfence-serialization-check-in-init_amd.patch b/queue-4.14/x86-cpu-fix-lfence-serialization-check-in-init_amd.patch new file mode 100644 index 00000000000..2c67f430995 --- /dev/null +++ b/queue-4.14/x86-cpu-fix-lfence-serialization-check-in-init_amd.patch @@ -0,0 +1,39 @@ +From rhythm.m.mahajan@oracle.com Wed Mar 15 12:38:00 2023 +From: Rhythm Mahajan +Date: Wed, 15 Mar 2023 03:40:15 -0700 +Subject: x86/cpu: Fix LFENCE serialization check in init_amd() +To: tglx@linutronix.de +Cc: rhythm.m.mahajan@oracle.com, mingo@redhat.com, hpa@zytor.com, bp@suse.de, gregkh@linuxfoundation.org, pawan.kumar.gupta@linux.intel.com, cascardo@canonical.com, surajjs@amazon.com, daniel.sneddon@linux.intel.com, peterz@infradead.org, stable@vger.kernel.org +Message-ID: <20230315104015.3607718-1-rhythm.m.mahajan@oracle.com> + +From: Rhythm Mahajan + +The commit: 3f235279828c ("x86/cpu: Restore AMD's DE_CFG MSR after resume") +which was backported from the upstream commit: 2632daebafd0 renamed the +MSR_F10H_DECFG_LFENCE_SERIALIZE macro to MSR_AMD64_DE_CFG_LFENCE_SERIALIZE. +The fix for 4.14 and 4.9 changed MSR_F10H_DECFG_LFENCE_SERIALIZE to +MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT in the init_amd() function, but should +have used MSR_AMD64_DE_CFG_LFENCE_SERIALIZE. This causes a discrepency in the +LFENCE serialization check in the init_amd() function. + +This causes a ~16% sysbench memory regression, when running: + sysbench --test=memory run + +Fixes: 3f235279828c ("x86/cpu: Restore AMD's DE_CFG MSR after resume") +Signed-off-by: Rhythm Mahajan +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/kernel/cpu/amd.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/x86/kernel/cpu/amd.c ++++ b/arch/x86/kernel/cpu/amd.c +@@ -950,7 +950,7 @@ static void init_amd(struct cpuinfo_x86 + * serializing. + */ + ret = rdmsrl_safe(MSR_AMD64_DE_CFG, &val); +- if (!ret && (val & MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)) { ++ if (!ret && (val & MSR_AMD64_DE_CFG_LFENCE_SERIALIZE)) { + /* A serializing LFENCE stops RDTSC speculation */ + set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); + } else { -- 2.47.3