From 56dfdf2da1cf6261eaeb4259dee27201f2800691 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Sun, 23 Nov 2025 18:53:43 +0000 Subject: [PATCH] MAINTAINERS: degrade RISC-V MISC SOC SUPPORT to Odd Fixes The SiFive and Canaan platforms are not being actively looked after at this point, but fixes for them would be applied if/when the patches appeared. Since they're now the only things in the RISC-V MISC SOC SUPPORT, mark them as Odd Fixes. I don't believe this is a functional change, it just represents what's actually happening - particularly since the Canaan k230 never built up enough steam to get merged and the new SiFive demo chips have been done in partnership with with other companies, e.g. Eswin, and will reside in their directories instead. Reviewed-by: Paul Walmsley Signed-off-by: Conor Dooley --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 4981224985b4f..72bfa33aa225d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22115,7 +22115,7 @@ F: include/soc/microchip/mpfs.h RISC-V MISC SOC SUPPORT M: Conor Dooley L: linux-riscv@lists.infradead.org -S: Maintained +S: Odd Fixes T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ F: arch/riscv/boot/dts/canaan/ F: arch/riscv/boot/dts/sifive/ -- 2.47.3