From 5a07192a042e60ce7415279a48aff8a932829f55 Mon Sep 17 00:00:00 2001 From: "mkdolata@us.ibm.com" Date: Tue, 7 Jan 2020 14:26:07 +0100 Subject: [PATCH] target/i386: Fix handling of k_gs_base register in 32-bit mode in gdbstub gdb-xml/i386-32bit.xml includes the k_gs_base register too, so we have to handle it even if TARGET_X86_64 is not defined. This is already done in x86_cpu_gdb_read_register, but not in x86_cpu_gdb_write_register where the incorrect return value causes all registers after it to be clobbered. Fixes https://bugs.launchpad.net/qemu/+bug/1857640. Signed-off-by: Marek Dolata Signed-off-by: Paolo Bonzini --- target/i386/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index aef25b70f10..572ead641ca 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -350,15 +350,15 @@ int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->segs[R_GS].base = ldl_p(mem_buf); return 4; -#ifdef TARGET_X86_64 case IDX_SEG_REGS + 8: +#ifdef TARGET_X86_64 if (env->hflags & HF_CS64_MASK) { env->kernelgsbase = ldq_p(mem_buf); return 8; } env->kernelgsbase = ldl_p(mem_buf); - return 4; #endif + return 4; case IDX_FP_REGS + 8: cpu_set_fpuc(env, ldl_p(mem_buf)); -- 2.39.5