From 61f7f488b524de2486e672d820bdd71e372da5db Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 30 Nov 2022 18:45:02 +0100 Subject: [PATCH] 5.10-stable patches added patches: drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch --- ...-for-gen12-video-and-compute-engines.patch | 39 +++++++++++++++++++ queue-5.10/series | 1 + 2 files changed, 40 insertions(+) create mode 100644 queue-5.10/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch diff --git a/queue-5.10/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch b/queue-5.10/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch new file mode 100644 index 00000000000..021548c2b17 --- /dev/null +++ b/queue-5.10/drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch @@ -0,0 +1,39 @@ +From 04aa64375f48a5d430b5550d9271f8428883e550 Mon Sep 17 00:00:00 2001 +From: Andrzej Hajda +Date: Mon, 14 Nov 2022 11:38:24 +0100 +Subject: drm/i915: fix TLB invalidation for Gen12 video and compute engines + +From: Andrzej Hajda + +commit 04aa64375f48a5d430b5550d9271f8428883e550 upstream. + +In case of Gen12 video and compute engines, TLB_INV registers are masked - +to modify one bit, corresponding bit in upper half of the register must +be enabled, otherwise nothing happens. + +CVE: CVE-2022-4139 +Suggested-by: Chris Wilson +Signed-off-by: Andrzej Hajda +Acked-by: Daniel Vetter +Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") +Cc: stable@vger.kernel.org +Signed-off-by: Linus Torvalds +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/gt/intel_gt.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/i915/gt/intel_gt.c ++++ b/drivers/gpu/drm/i915/gt/intel_gt.c +@@ -745,6 +745,11 @@ void intel_gt_invalidate_tlbs(struct int + if (!i915_mmio_reg_offset(rb.reg)) + continue; + ++ if (GRAPHICS_VER(i915) == 12 && (engine->class == VIDEO_DECODE_CLASS || ++ engine->class == VIDEO_ENHANCEMENT_CLASS || ++ engine->class == COMPUTE_CLASS)) ++ rb.bit = _MASKED_BIT_ENABLE(rb.bit); ++ + intel_uncore_write_fw(uncore, rb.reg, rb.bit); + } + diff --git a/queue-5.10/series b/queue-5.10/series index 8a0f25dcb34..b85d60375cf 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -159,3 +159,4 @@ btrfs-free-btrfs_path-before-copying-subvol-info-to-userspace.patch btrfs-sysfs-normalize-the-error-handling-branch-in-btrfs_init_sysfs.patch drm-amd-dc-dce120-fix-audio-register-mapping-stop-triggering-kasan.patch drm-amdgpu-always-register-an-mmu-notifier-for-userptr.patch +drm-i915-fix-tlb-invalidation-for-gen12-video-and-compute-engines.patch -- 2.47.3