From 64566e35757faded57a65d65e84b5ca95974ee19 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Fri, 22 Aug 2025 14:39:52 +0800 Subject: [PATCH] arm64: dts: rockchip: Add DP1 for rk3588 The DP1 is compliant with the DisplayPort Specification Version 1.4, and share the USBDP combo PHY1 with USB 3.1 HOST1 controller. Signed-off-by: Andy Yan Reviewed-by: Sebastian Reichel Link: https://lore.kernel.org/r/20250822063959.692098-9-andyshrk@163.com Signed-off-by: Heiko Stuebner --- .../arm64/boot/dts/rockchip/rk3588-extra.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi index 90414486e466f..6e5a58428bbab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -210,6 +210,36 @@ status = "disabled"; }; + dp1: dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = ; + assigned-clocks = <&cru CLK_AUX16M_1>; + assigned-clock-rates = <16000000>; + clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, + <&cru CLK_DP1>, <&cru MCLK_I2S8_8CH_TX>, + <&cru MCLK_SPDIF5_DP1>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + phys = <&usbdp_phy1 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_DP1>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dp1_in: port@0 { + reg = <0>; + }; + + dp1_out: port@1 { + reg = <1>; + }; + }; + }; + hdmi1: hdmi@fdea0000 { compatible = "rockchip,rk3588-dw-hdmi-qp"; reg = <0x0 0xfdea0000 0x0 0x20000>; -- 2.47.3