From 6bb68a70f010e785514e447d3b48c683dd9d3c30 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Fri, 11 May 2018 17:47:06 +0200 Subject: [PATCH] 4.9-stable patches added patches: arm64-add-work-around-for-arm-cortex-a55-erratum-1024718.patch --- ...d-for-arm-cortex-a55-erratum-1024718.patch | 163 ++++++++++++++++++ queue-4.9/series | 1 + 2 files changed, 164 insertions(+) create mode 100644 queue-4.9/arm64-add-work-around-for-arm-cortex-a55-erratum-1024718.patch diff --git a/queue-4.9/arm64-add-work-around-for-arm-cortex-a55-erratum-1024718.patch b/queue-4.9/arm64-add-work-around-for-arm-cortex-a55-erratum-1024718.patch new file mode 100644 index 00000000000..04e00791a0d --- /dev/null +++ b/queue-4.9/arm64-add-work-around-for-arm-cortex-a55-erratum-1024718.patch @@ -0,0 +1,163 @@ +From ece1397cbc89c51914fae1aec729539cfd8bd62b Mon Sep 17 00:00:00 2001 +From: Suzuki K Poulose +Date: Mon, 26 Mar 2018 15:12:49 +0100 +Subject: arm64: Add work around for Arm Cortex-A55 Erratum 1024718 + +From: Suzuki K Poulose + +commit ece1397cbc89c51914fae1aec729539cfd8bd62b upstream. + +Some variants of the Arm Cortex-55 cores (r0p0, r0p1, r1p0) suffer +from an erratum 1024718, which causes incorrect updates when DBM/AP +bits in a page table entry is modified without a break-before-make +sequence. The work around is to skip enabling the hardware DBM feature +on the affected cores. The hardware Access Flag management features +is not affected. There are some other cores suffering from this +errata, which could be added to the midr_list to trigger the work +around. + +Cc: Catalin Marinas +Cc: ckadabi@codeaurora.org +Reviewed-by: Dave Martin +Signed-off-by: Suzuki K Poulose +Signed-off-by: Will Deacon +Signed-off-by: Greg Kroah-Hartman + + +--- + Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 14 +++++++++++ + arch/arm64/include/asm/assembler.h | 40 +++++++++++++++++++++++++++++++++ + arch/arm64/include/asm/cputype.h | 5 ++++ + arch/arm64/mm/proc.S | 5 ++++ + 5 files changed, 65 insertions(+) + +--- a/Documentation/arm64/silicon-errata.txt ++++ b/Documentation/arm64/silicon-errata.txt +@@ -54,6 +54,7 @@ stable kernels. + | ARM | Cortex-A57 | #852523 | N/A | + | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 | + | ARM | Cortex-A72 | #853709 | N/A | ++| ARM | Cortex-A55 | #1024718 | ARM64_ERRATUM_1024718 | + | ARM | MMU-500 | #841119,#826419 | N/A | + | | | | | + | Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 | +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -427,6 +427,20 @@ config ARM64_ERRATUM_843419 + + If unsure, say Y. + ++config ARM64_ERRATUM_1024718 ++ bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update" ++ default y ++ help ++ This option adds work around for Arm Cortex-A55 Erratum 1024718. ++ ++ Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect ++ update of the hardware dirty bit when the DBM/AP bits are updated ++ without a break-before-make. The work around is to disable the usage ++ of hardware DBM locally on the affected cores. CPUs not affected by ++ erratum will continue to use the feature. ++ ++ If unsure, say Y. ++ + config CAVIUM_ERRATUM_22375 + bool "Cavium erratum 22375, 24313" + default y +--- a/arch/arm64/include/asm/assembler.h ++++ b/arch/arm64/include/asm/assembler.h +@@ -25,6 +25,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -435,4 +436,43 @@ alternative_endif + and \phys, \pte, #(((1 << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT) + .endm + ++/* ++ * Check the MIDR_EL1 of the current CPU for a given model and a range of ++ * variant/revision. See asm/cputype.h for the macros used below. ++ * ++ * model: MIDR_CPU_MODEL of CPU ++ * rv_min: Minimum of MIDR_CPU_VAR_REV() ++ * rv_max: Maximum of MIDR_CPU_VAR_REV() ++ * res: Result register. ++ * tmp1, tmp2, tmp3: Temporary registers ++ * ++ * Corrupts: res, tmp1, tmp2, tmp3 ++ * Returns: 0, if the CPU id doesn't match. Non-zero otherwise ++ */ ++ .macro cpu_midr_match model, rv_min, rv_max, res, tmp1, tmp2, tmp3 ++ mrs \res, midr_el1 ++ mov_q \tmp1, (MIDR_REVISION_MASK | MIDR_VARIANT_MASK) ++ mov_q \tmp2, MIDR_CPU_MODEL_MASK ++ and \tmp3, \res, \tmp2 // Extract model ++ and \tmp1, \res, \tmp1 // rev & variant ++ mov_q \tmp2, \model ++ cmp \tmp3, \tmp2 ++ cset \res, eq ++ cbz \res, .Ldone\@ // Model matches ? ++ ++ .if (\rv_min != 0) // Skip min check if rv_min == 0 ++ mov_q \tmp3, \rv_min ++ cmp \tmp1, \tmp3 ++ cset \res, ge ++ .endif // \rv_min != 0 ++ /* Skip rv_max check if rv_min == rv_max && rv_min != 0 */ ++ .if ((\rv_min != \rv_max) || \rv_min == 0) ++ mov_q \tmp2, \rv_max ++ cmp \tmp1, \tmp2 ++ cset \tmp2, le ++ and \res, \res, \tmp2 ++ .endif ++.Ldone\@: ++ .endm ++ + #endif /* __ASM_ASSEMBLER_H */ +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -56,6 +56,9 @@ + (0xf << MIDR_ARCHITECTURE_SHIFT) | \ + ((partnum) << MIDR_PARTNUM_SHIFT)) + ++#define MIDR_CPU_VAR_REV(var, rev) \ ++ (((var) << MIDR_VARIANT_SHIFT) | (rev)) ++ + #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ + MIDR_ARCHITECTURE_MASK) + +@@ -74,6 +77,7 @@ + + #define ARM_CPU_PART_AEM_V8 0xD0F + #define ARM_CPU_PART_FOUNDATION 0xD00 ++#define ARM_CPU_PART_CORTEX_A55 0xD05 + #define ARM_CPU_PART_CORTEX_A57 0xD07 + #define ARM_CPU_PART_CORTEX_A72 0xD08 + #define ARM_CPU_PART_CORTEX_A53 0xD03 +@@ -89,6 +93,7 @@ + #define BRCM_CPU_PART_VULCAN 0x516 + + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) ++#define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) + #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) + #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) + #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) +--- a/arch/arm64/mm/proc.S ++++ b/arch/arm64/mm/proc.S +@@ -425,6 +425,11 @@ ENTRY(__cpu_setup) + cbz x9, 2f + cmp x9, #2 + b.lt 1f ++#ifdef CONFIG_ARM64_ERRATUM_1024718 ++ /* Disable hardware DBM on Cortex-A55 r0p0, r0p1 & r1p0 */ ++ cpu_midr_match MIDR_CORTEX_A55, MIDR_CPU_VAR_REV(0, 0), MIDR_CPU_VAR_REV(1, 0), x1, x2, x3, x4 ++ cbnz x1, 1f ++#endif + orr x10, x10, #TCR_HD // hardware Dirty flag update + 1: orr x10, x10, #TCR_HA // hardware Access flag update + 2: diff --git a/queue-4.9/series b/queue-4.9/series index 3b20e6aef4d..53fbea91507 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -13,3 +13,4 @@ tcp-fix-tcp_repair_queue-bound-checking.patch bdi-fix-oops-in-wb_workfn.patch kvm-ppc-book3s-hv-fix-trap-number-return-from-__kvmppc_vcore_entry.patch f2fs-fix-a-dead-loop-in-f2fs_fiemap.patch +arm64-add-work-around-for-arm-cortex-a55-erratum-1024718.patch -- 2.47.3