From 6ca7155a8c8d88e5372f0ba337c33e86edbcb295 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 6 Jan 2022 07:39:34 +1000 Subject: [PATCH] target/riscv: Mark the Hypervisor extension as non experimental The Hypervisor spec is now frozen, so remove the experimental tag. Signed-off-by: Alistair Francis Reviewed-by: Anup Patel Reviewed-by: Bin Meng Message-Id: <20220105213937.1113508-6-alistair.francis@opensource.wdc.com> --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bced..9ea67bedd3e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -627,6 +627,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), @@ -645,7 +646,6 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), - DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), -- 2.39.5