From 6e1a981cef99d7a53f7ed1ad1ddaf0bfc8506cbd Mon Sep 17 00:00:00 2001 From: Hongren Zheng Date: Tue, 2 Sep 2025 22:00:10 +0800 Subject: [PATCH] RISC-V: Use address for vlenb CSR Reviewed-by: Matt Caswell Reviewed-by: Paul Dale Reviewed-by: Tomas Mraz (Merged from https://github.com/openssl/openssl/pull/28422) (cherry picked from commit 1a278e765a5167368268cd3034649c2c5d504c11) --- crypto/riscv32cpuid.pl | 3 ++- crypto/riscv64cpuid.pl | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/crypto/riscv32cpuid.pl b/crypto/riscv32cpuid.pl index 5ee7df0ea63..b693412b600 100644 --- a/crypto/riscv32cpuid.pl +++ b/crypto/riscv32cpuid.pl @@ -94,7 +94,8 @@ $code .= <<___; .globl riscv_vlen_asm .type riscv_vlen_asm,\@function riscv_vlen_asm: - csrr $ret, vlenb + # 0xc22 is CSR vlenb + csrr $ret, 0xc22 slli $ret, $ret, 3 ret .size riscv_vlen_asm,.-riscv_vlen_asm diff --git a/crypto/riscv64cpuid.pl b/crypto/riscv64cpuid.pl index 5dcdc5c584c..59e78534817 100644 --- a/crypto/riscv64cpuid.pl +++ b/crypto/riscv64cpuid.pl @@ -94,7 +94,8 @@ $code .= <<___; .globl riscv_vlen_asm .type riscv_vlen_asm,\@function riscv_vlen_asm: - csrr $ret, vlenb + # 0xc22 is CSR vlenb + csrr $ret, 0xc22 slli $ret, $ret, 3 ret .size riscv_vlen_asm,.-riscv_vlen_asm -- 2.47.3