From 707ea7ab4d55e0d907f72280eb2e4d376efeddf7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?C=C3=A9dric=20Le=20Goater?= Date: Wed, 2 Mar 2022 06:51:39 +0100 Subject: [PATCH] pnv/xive2: Introduce new capability bits MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit These bits control the availability of interrupt features : StoreEOI, PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE exploitation mode. These bits can be set at early boot time of the system to activate/deactivate a feature for testing purposes. The default value should be '1'. The 'XIVE exploitation mode' bit is a software bit that skiboot could use to disable the XIVE OS interface and propose a P8 style XICS interface instead. There are no plans for that for the moment. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/intc/pnv_xive2.c | 4 ++-- hw/intc/pnv_xive2_regs.h | 5 +++++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 1fa89c77928..e22049424f3 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1709,9 +1709,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = { }; /* - * POWER10 default capabilities: 0x2000120076f00000 + * POWER10 default capabilities: 0x2000120076f000FC */ -#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000 +#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC /* * POWER10 default configuration: 0x0030000033000000 diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h index d45d17cedcc..a46e5133b56 100644 --- a/hw/intc/pnv_xive2_regs.h +++ b/hw/intc/pnv_xive2_regs.h @@ -31,6 +31,11 @@ #define CQ_XIVE_CAP_VP_INT_PRIO_8 3 #define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13) +#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56) +#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57) +#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58) +#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59) + /* XIVE2 Configuration */ #define X_CQ_XIVE_CFG 0x03 #define CQ_XIVE_CFG 0x018 -- 2.39.5