From 717a5eb34e54e0da11cb89b0f964b7ff79eefd30 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 3 Oct 2019 17:24:45 +0200 Subject: [PATCH] 5.3-stable patches added patches: drm-amd-display-add-missing-hbm-support-and-raise-vega20-s-uclk.patch drm-amd-display-dce11.x-dce12-update-formula-input.patch drm-amd-display-restore-backlight-brightness-after-system-resume.patch drm-amdgpu-display-fix-64-bit-divide.patch --- ...-hbm-support-and-raise-vega20-s-uclk.patch | 68 ++++++++ ...y-dce11.x-dce12-update-formula-input.patch | 153 ++++++++++++++++++ ...light-brightness-after-system-resume.patch | 40 +++++ ...drm-amdgpu-display-fix-64-bit-divide.patch | 32 ++++ queue-5.3/series | 4 + 5 files changed, 297 insertions(+) create mode 100644 queue-5.3/drm-amd-display-add-missing-hbm-support-and-raise-vega20-s-uclk.patch create mode 100644 queue-5.3/drm-amd-display-dce11.x-dce12-update-formula-input.patch create mode 100644 queue-5.3/drm-amd-display-restore-backlight-brightness-after-system-resume.patch create mode 100644 queue-5.3/drm-amdgpu-display-fix-64-bit-divide.patch diff --git a/queue-5.3/drm-amd-display-add-missing-hbm-support-and-raise-vega20-s-uclk.patch b/queue-5.3/drm-amd-display-add-missing-hbm-support-and-raise-vega20-s-uclk.patch new file mode 100644 index 00000000000..a420a88b1ab --- /dev/null +++ b/queue-5.3/drm-amd-display-add-missing-hbm-support-and-raise-vega20-s-uclk.patch @@ -0,0 +1,68 @@ +From c02d6a161395dfc0c2fdabb9e976a229017288d8 Mon Sep 17 00:00:00 2001 +From: Zhan Liu +Date: Thu, 22 Aug 2019 14:54:18 -0400 +Subject: drm/amd/display: Add missing HBM support and raise Vega20's uclk. + +From: Zhan Liu + +commit c02d6a161395dfc0c2fdabb9e976a229017288d8 upstream. + +[Why] +When more than 2 displays are connected to the graphics card, +only the minimum memory clock is needed. However, when more +displays are connected, the minimum memory clock is not +sufficient enough to support the overwhelming bandwidth. +System will hang under this circumstance. + +Also, the old code didn't address HBM cards, which has 2 +pseudo channels. We need to add the HBM part here. + +[How] +When graphics card connects to 2 or more displays, +switch to high memory clock. Also, choose memory +multiplier based on whether its regular DRAM or HBM. + +Signed-off-by: Zhan Liu +Reviewed-by: Roman Li +Acked-by: Leo Li +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 18 ++++++++-- + 1 file changed, 16 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -174,6 +174,10 @@ void dce11_pplib_apply_display_requireme + struct dc_state *context) + { + struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; ++ int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; ++ ++ if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) ++ memory_type_multiplier = MEMORY_TYPE_HBM; + + pp_display_cfg->all_displays_in_sync = + context->bw_ctx.bw.dce.all_displays_in_sync; +@@ -186,8 +190,18 @@ void dce11_pplib_apply_display_requireme + pp_display_cfg->cpu_pstate_separation_time = + context->bw_ctx.bw.dce.blackout_recovery_time_us; + +- pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz +- / MEMORY_TYPE_MULTIPLIER_CZ; ++ /* ++ * TODO: determine whether the bandwidth has reached memory's limitation ++ * , then change minimum memory clock based on real-time bandwidth ++ * limitation. ++ */ ++ if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) { ++ pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz, ++ (uint32_t) (dc->bw_vbios->high_yclk.value / memory_type_multiplier / 10000)); ++ } else { ++ pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz ++ / memory_type_multiplier; ++ } + + pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( + dc, diff --git a/queue-5.3/drm-amd-display-dce11.x-dce12-update-formula-input.patch b/queue-5.3/drm-amd-display-dce11.x-dce12-update-formula-input.patch new file mode 100644 index 00000000000..70b3a73928e --- /dev/null +++ b/queue-5.3/drm-amd-display-dce11.x-dce12-update-formula-input.patch @@ -0,0 +1,153 @@ +From c46e5df4ac898108da66a880c4e18f69c74f6c1b Mon Sep 17 00:00:00 2001 +From: Charlene Liu +Date: Tue, 20 Aug 2019 20:33:46 -0400 +Subject: drm/amd/display: dce11.x /dce12 update formula input + +From: Charlene Liu + +commit c46e5df4ac898108da66a880c4e18f69c74f6c1b upstream. + +[Description] +1. OUTSTANDING_REQUEST_LIMIT update from 0xFF to 0x1F (HW doc update) +2. using memory type to convert UMC's MCLK to Yclk. + +Signed-off-by: Charlene Liu +Reviewed-by: Dmytro Laktyushkin +Acked-by: Bhawanpreet Lakha +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 7 +++- + drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 4 +- + drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 16 ++++++---- + drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 11 +++++- + drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 + + 5 files changed, 27 insertions(+), 13 deletions(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -98,11 +98,14 @@ uint32_t dce110_get_min_vblank_time_us(c + struct dc_stream_state *stream = context->streams[j]; + uint32_t vertical_blank_in_pixels = 0; + uint32_t vertical_blank_time = 0; ++ uint32_t vertical_total_min = stream->timing.v_total; ++ struct dc_crtc_timing_adjust adjust = stream->adjust; ++ if (adjust.v_total_max != adjust.v_total_min) ++ vertical_total_min = adjust.v_total_min; + + vertical_blank_in_pixels = stream->timing.h_total * +- (stream->timing.v_total ++ (vertical_total_min + - stream->timing.v_addressable); +- + vertical_blank_time = vertical_blank_in_pixels + * 10000 / stream->timing.pix_clk_100hz; + +--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c ++++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +@@ -148,7 +148,7 @@ static void dce_mi_program_pte_vm( + pte->min_pte_before_flip_horiz_scan; + + REG_UPDATE(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, +- GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0xff); ++ GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, 0x7f); + + REG_UPDATE_3(DVMM_PTE_CONTROL, + DVMM_PAGE_WIDTH, page_width, +@@ -157,7 +157,7 @@ static void dce_mi_program_pte_vm( + + REG_UPDATE_2(DVMM_PTE_ARB_CONTROL, + DVMM_PTE_REQ_PER_CHUNK, pte->pte_req_per_chunk, +- DVMM_MAX_PTE_REQ_OUTSTANDING, 0xff); ++ DVMM_MAX_PTE_REQ_OUTSTANDING, 0x7f); + } + + static void program_urgency_watermark( +--- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +@@ -987,6 +987,10 @@ static void bw_calcs_data_update_from_pp + struct dm_pp_clock_levels_with_latency mem_clks = {0}; + struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; + struct dm_pp_clock_levels clks = {0}; ++ int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; ++ ++ if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) ++ memory_type_multiplier = MEMORY_TYPE_HBM; + + /*do system clock TODO PPLIB: after PPLIB implement, + * then remove old way +@@ -1026,12 +1030,12 @@ static void bw_calcs_data_update_from_pp + &clks); + + dc->bw_vbios->low_yclk = bw_frc_to_fixed( +- clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER_CZ, 1000); ++ clks.clocks_in_khz[0] * memory_type_multiplier, 1000); + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( +- clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER_CZ, ++ clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, + 1000); + dc->bw_vbios->high_yclk = bw_frc_to_fixed( +- clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER_CZ, ++ clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, + 1000); + + return; +@@ -1067,12 +1071,12 @@ static void bw_calcs_data_update_from_pp + * YCLK = UMACLK*m_memoryTypeMultiplier + */ + dc->bw_vbios->low_yclk = bw_frc_to_fixed( +- mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); ++ mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, + 1000); + dc->bw_vbios->high_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, + 1000); + + /* Now notify PPLib/SMU about which Watermarks sets they should select +--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ++++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +@@ -847,6 +847,8 @@ static void bw_calcs_data_update_from_pp + int i; + unsigned int clk; + unsigned int latency; ++ /*original logic in dal3*/ ++ int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; + + /*do system clock*/ + if (!dm_pp_get_clock_levels_by_type_with_latency( +@@ -905,13 +907,16 @@ static void bw_calcs_data_update_from_pp + * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): + * YCLK = UMACLK*m_memoryTypeMultiplier + */ ++ if (dc->bw_vbios->memory_type == bw_def_hbm) ++ memory_type_multiplier = MEMORY_TYPE_HBM; ++ + dc->bw_vbios->low_yclk = bw_frc_to_fixed( +- mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, 1000); ++ mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); + dc->bw_vbios->mid_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, + 1000); + dc->bw_vbios->high_yclk = bw_frc_to_fixed( +- mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER_CZ, ++ mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, + 1000); + + /* Now notify PPLib/SMU about which Watermarks sets they should select +--- a/drivers/gpu/drm/amd/display/dc/inc/resource.h ++++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h +@@ -31,6 +31,8 @@ + #include "dm_pp_smu.h" + + #define MEMORY_TYPE_MULTIPLIER_CZ 4 ++#define MEMORY_TYPE_HBM 2 ++ + + enum dce_version resource_parse_asic_id( + struct hw_asic_id asic_id); diff --git a/queue-5.3/drm-amd-display-restore-backlight-brightness-after-system-resume.patch b/queue-5.3/drm-amd-display-restore-backlight-brightness-after-system-resume.patch new file mode 100644 index 00000000000..d37bd47b5ad --- /dev/null +++ b/queue-5.3/drm-amd-display-restore-backlight-brightness-after-system-resume.patch @@ -0,0 +1,40 @@ +From bb264220d9316f6bd7c1fd84b8da398c93912931 Mon Sep 17 00:00:00 2001 +From: Kai-Heng Feng +Date: Mon, 2 Sep 2019 16:33:42 +0800 +Subject: drm/amd/display: Restore backlight brightness after system resume + +From: Kai-Heng Feng + +commit bb264220d9316f6bd7c1fd84b8da398c93912931 upstream. + +Laptops with AMD APU doesn't restore display backlight brightness after +system resume. + +This issue started when DC was introduced. + +Let's use BL_CORE_SUSPENDRESUME so the backlight core calls +update_status callback after system resume to restore the backlight +level. + +Tested on Dell Inspiron 3180 (Stoney Ridge) and Dell Latitude 5495 +(Raven Ridge). + +Cc: +Signed-off-by: Kai-Heng Feng +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -2107,6 +2107,7 @@ static int amdgpu_dm_backlight_get_brigh + } + + static const struct backlight_ops amdgpu_dm_backlight_ops = { ++ .options = BL_CORE_SUSPENDRESUME, + .get_brightness = amdgpu_dm_backlight_get_brightness, + .update_status = amdgpu_dm_backlight_update_status, + }; diff --git a/queue-5.3/drm-amdgpu-display-fix-64-bit-divide.patch b/queue-5.3/drm-amdgpu-display-fix-64-bit-divide.patch new file mode 100644 index 00000000000..698d3e2aa35 --- /dev/null +++ b/queue-5.3/drm-amdgpu-display-fix-64-bit-divide.patch @@ -0,0 +1,32 @@ +From dd9212a885ca4a95443905c7c3781122a4d664e8 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 20 Sep 2019 15:13:24 -0500 +Subject: drm/amdgpu/display: fix 64 bit divide + +From: Alex Deucher + +commit dd9212a885ca4a95443905c7c3781122a4d664e8 upstream. + +Use proper helper for 32 bit. + +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c ++++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c +@@ -197,7 +197,9 @@ void dce11_pplib_apply_display_requireme + */ + if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) { + pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz, +- (uint32_t) (dc->bw_vbios->high_yclk.value / memory_type_multiplier / 10000)); ++ (uint32_t) div64_s64( ++ div64_s64(dc->bw_vbios->high_yclk.value, ++ memory_type_multiplier), 10000)); + } else { + pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz + / memory_type_multiplier; diff --git a/queue-5.3/series b/queue-5.3/series index 5e4e482ed73..c114c31c54a 100644 --- a/queue-5.3/series +++ b/queue-5.3/series @@ -335,6 +335,10 @@ hwrng-core-don-t-wait-on-add_early_randomness.patch i2c-riic-clear-nack-in-tend-isr.patch cifs-fix-max-ea-value-size.patch cifs-fix-oplock-handling-for-smb-2.1-protocols.patch +drm-amd-display-restore-backlight-brightness-after-system-resume.patch +drm-amd-display-dce11.x-dce12-update-formula-input.patch +drm-amd-display-add-missing-hbm-support-and-raise-vega20-s-uclk.patch +drm-amdgpu-display-fix-64-bit-divide.patch md-raid0-avoid-raid0-data-corruption-due-to-layout-c.patch mt76-mt7615-always-release-sem-in-mt7615_load_patch.patch mt76-mt7615-fix-mt7615-firmware-path-definitions.patch -- 2.47.2