From 7261f2a7a75ab9be4aa3f8a7896f21a39df74006 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 11 Dec 2024 10:29:50 -0600 Subject: [PATCH] target/arm: Fix decode of fp16 vector fabs, fneg, fsqrt These opcodes are only supported as vector operations, not as advsimd scalar. Set only_in_vector, and remove the unreachable implementation of scalar fneg. Reported-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20241211163036.2297116-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index a99f3d0d135..3c1784593a4 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10816,10 +10816,13 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) break; case 0x2f: /* FABS */ case 0x6f: /* FNEG */ + only_in_vector = true; need_fpst = false; break; case 0x7d: /* FRSQRTE */ + break; case 0x7f: /* FSQRT (vector) */ + only_in_vector = true; break; default: unallocated_encoding(s); @@ -10877,9 +10880,6 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ gen_helper_advsimd_f16touinth(tcg_res, tcg_op, tcg_fpstatus); break; - case 0x6f: /* FNEG */ - tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); - break; case 0x7d: /* FRSQRTE */ gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); break; -- 2.39.5