From 73c09edb74ff5748c7e85d73734cd3fc255005aa Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 1 Mar 2021 15:22:53 +0100 Subject: [PATCH] 5.4-stable patches added patches: drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch --- ...-reject-446-480mhz-hdmi-clock-on-glk.patch | 46 +++++++++++++++++++ queue-5.4/series | 1 + 2 files changed, 47 insertions(+) create mode 100644 queue-5.4/drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch diff --git a/queue-5.4/drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch b/queue-5.4/drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch new file mode 100644 index 00000000000..2f443668fee --- /dev/null +++ b/queue-5.4/drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch @@ -0,0 +1,46 @@ +From 7a6c6243b44a439bda4bf099032be35ebcf53406 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Wed, 3 Feb 2021 11:30:44 +0200 +Subject: drm/i915: Reject 446-480MHz HDMI clock on GLK +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Ville Syrjälä + +commit 7a6c6243b44a439bda4bf099032be35ebcf53406 upstream. + +The BXT/GLK DPLL can't generate certain frequencies. We already +reject the 233-240MHz range on both. But on GLK the DPLL max +frequency was bumped from 300MHz to 594MHz, so now we get to +also worry about the 446-480MHz range (double the original +problem range). Reject any frequency within the higher +problematic range as well. + +Cc: stable@vger.kernel.org +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3000 +Signed-off-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20210203093044.30532-1-ville.syrjala@linux.intel.com +Reviewed-by: Mika Kahola +(cherry picked from commit 41751b3e5c1ac656a86f8d45a8891115281b729e) +Signed-off-by: Rodrigo Vivi +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/intel_hdmi.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/display/intel_hdmi.c ++++ b/drivers/gpu/drm/i915/display/intel_hdmi.c +@@ -2129,7 +2129,11 @@ hdmi_port_clock_valid(struct intel_hdmi + if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) + return MODE_CLOCK_HIGH; + +- /* BXT DPLL can't generate 223-240 MHz */ ++ /* GLK DPLL can't generate 446-480 MHz */ ++ if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000) ++ return MODE_CLOCK_RANGE; ++ ++ /* BXT/GLK DPLL can't generate 223-240 MHz */ + if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) + return MODE_CLOCK_RANGE; + diff --git a/queue-5.4/series b/queue-5.4/series index 237a4fcbc94..46727339670 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -327,3 +327,4 @@ dm-era-fix-bitset-memory-leaks.patch dm-era-use-correct-value-size-in-equality-function-of-writeset-tree.patch dm-era-reinitialize-bitset-cache-before-digesting-a-new-writeset.patch dm-era-only-resize-metadata-in-preresume.patch +drm-i915-reject-446-480mhz-hdmi-clock-on-glk.patch -- 2.47.3