From 753a8400a467c0c80cb6cc45355d33ef6659680f Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 15 Sep 2015 15:10:09 -0700 Subject: [PATCH] 4.2-stable patches added patches: drm-amdgpu-atom-send-out-the-full-aux-address.patch drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch drm-amdgpu-fix-one-warning-message.patch drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch drm-i915-allow-dsi-dual-link-to-be-configured-on-any-pipe.patch drm-i915-always-mark-the-object-as-dirty-when-used-by-the-gpu.patch drm-i915-preserve-ssc-earlier.patch drm-qxl-validate-monitors-config-modes.patch drm-radeon-atom-send-out-the-full-aux-address.patch drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch drm-radeon-native-send-out-the-full-aux-address.patch --- ...u-atom-send-out-the-full-aux-address.patch | 40 +++++ ...layport-on-hpd-until-we-get-the-dpcd.patch | 34 ++++ ...ring-allocation-for-bus-addresses-v2.patch | 68 ++++++++ .../drm-amdgpu-fix-one-warning-message.patch | 39 +++++ ...pu-fix-typo-in-dce10-watermark-setup.patch | 31 ++++ ...pu-fix-typo-in-dce11-watermark-setup.patch | 31 ++++ ...al-link-to-be-configured-on-any-pipe.patch | 58 +++++++ ...object-as-dirty-when-used-by-the-gpu.patch | 58 +++++++ queue-4.2/drm-i915-preserve-ssc-earlier.patch | 117 ++++++++++++++ ...m-qxl-validate-monitors-config-modes.patch | 147 ++++++++++++++++++ ...n-atom-send-out-the-full-aux-address.patch | 39 +++++ ...uantization_range-for-pre-dce5-asics.patch | 47 ++++++ ...native-send-out-the-full-aux-address.patch | 40 +++++ queue-4.2/series | 13 ++ 14 files changed, 762 insertions(+) create mode 100644 queue-4.2/drm-amdgpu-atom-send-out-the-full-aux-address.patch create mode 100644 queue-4.2/drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch create mode 100644 queue-4.2/drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch create mode 100644 queue-4.2/drm-amdgpu-fix-one-warning-message.patch create mode 100644 queue-4.2/drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch create mode 100644 queue-4.2/drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch create mode 100644 queue-4.2/drm-i915-allow-dsi-dual-link-to-be-configured-on-any-pipe.patch create mode 100644 queue-4.2/drm-i915-always-mark-the-object-as-dirty-when-used-by-the-gpu.patch create mode 100644 queue-4.2/drm-i915-preserve-ssc-earlier.patch create mode 100644 queue-4.2/drm-qxl-validate-monitors-config-modes.patch create mode 100644 queue-4.2/drm-radeon-atom-send-out-the-full-aux-address.patch create mode 100644 queue-4.2/drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch create mode 100644 queue-4.2/drm-radeon-native-send-out-the-full-aux-address.patch diff --git a/queue-4.2/drm-amdgpu-atom-send-out-the-full-aux-address.patch b/queue-4.2/drm-amdgpu-atom-send-out-the-full-aux-address.patch new file mode 100644 index 00000000000..0878cb16a18 --- /dev/null +++ b/queue-4.2/drm-amdgpu-atom-send-out-the-full-aux-address.patch @@ -0,0 +1,40 @@ +From e39daf2c63518a8ce92e3ad5caa04097524b3585 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 31 Aug 2015 11:08:44 -0400 +Subject: drm/amdgpu/atom: Send out the full AUX address +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit e39daf2c63518a8ce92e3ad5caa04097524b3585 upstream. + +AUX addresses are 20 bits long. Send out the entire address instead of +just the low 16 bits. + +Port of: +drm/radeon/atom: Send out the full AUX address +to amdgpu + +Reviewed-by: Jammy Zhou +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c ++++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +@@ -139,7 +139,8 @@ amdgpu_atombios_dp_aux_transfer(struct d + + tx_buf[0] = msg->address & 0xff; + tx_buf[1] = msg->address >> 8; +- tx_buf[2] = msg->request << 4; ++ tx_buf[2] = (msg->request << 4) | ++ ((msg->address >> 16) & 0xf); + tx_buf[3] = msg->size ? (msg->size - 1) : 0; + + switch (msg->request & ~DP_AUX_I2C_MOT) { diff --git a/queue-4.2/drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch b/queue-4.2/drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch new file mode 100644 index 00000000000..f830dc1e5af --- /dev/null +++ b/queue-4.2/drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch @@ -0,0 +1,34 @@ +From a887adadb7b9ef9eb4ee48e4ad575aefcfd1db14 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Fri, 21 Aug 2015 18:07:38 -0400 +Subject: drm/amdgpu: Don't link train DisplayPort on HPD until we get the dpcd + +From: Alex Deucher + +commit a887adadb7b9ef9eb4ee48e4ad575aefcfd1db14 upstream. + +This is a port of: +DRM - radeon: Don't link train DisplayPort on HPD until we get the dpcd +to amdgpu. + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +@@ -75,6 +75,11 @@ void amdgpu_connector_hotplug(struct drm + if (!amdgpu_display_hpd_sense(adev, amdgpu_connector->hpd.hpd)) { + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + } else if (amdgpu_atombios_dp_needs_link_train(amdgpu_connector)) { ++ /* Don't try to start link training before we ++ * have the dpcd */ ++ if (!amdgpu_atombios_dp_get_dpcd(amdgpu_connector)) ++ return; ++ + /* set it to OFF so that drm_helper_connector_dpms() + * won't return immediately since the current state + * is ON at this point. diff --git a/queue-4.2/drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch b/queue-4.2/drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch new file mode 100644 index 00000000000..4001021a886 --- /dev/null +++ b/queue-4.2/drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch @@ -0,0 +1,68 @@ +From 52293c67f1e7542a6dc61037d83c266e216bef27 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 24 Aug 2015 22:46:13 -0400 +Subject: drm/amdgpu: fix IH ring allocation for bus addresses (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit 52293c67f1e7542a6dc61037d83c266e216bef27 upstream. + +Use pci_alloc_consistent rather than kzalloc since we +need 256 byte aligned memory for the ring buffer. + +v2: fix copy paste typo in free function noticed +by Jammy. + +bug: +https://bugs.freedesktop.org/show_bug.cgi?id=91749 + +Reviewed-by: Christian König +Reviewed-by: Jammy Zhou +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c | 20 +++++++------------- + 1 file changed, 7 insertions(+), 13 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c +@@ -97,18 +97,12 @@ int amdgpu_ih_ring_init(struct amdgpu_de + /* add 8 bytes for the rptr/wptr shadows and + * add them to the end of the ring allocation. + */ +- adev->irq.ih.ring = kzalloc(adev->irq.ih.ring_size + 8, GFP_KERNEL); ++ adev->irq.ih.ring = pci_alloc_consistent(adev->pdev, ++ adev->irq.ih.ring_size + 8, ++ &adev->irq.ih.rb_dma_addr); + if (adev->irq.ih.ring == NULL) + return -ENOMEM; +- adev->irq.ih.rb_dma_addr = pci_map_single(adev->pdev, +- (void *)adev->irq.ih.ring, +- adev->irq.ih.ring_size, +- PCI_DMA_BIDIRECTIONAL); +- if (pci_dma_mapping_error(adev->pdev, adev->irq.ih.rb_dma_addr)) { +- dev_err(&adev->pdev->dev, "Failed to DMA MAP the IH RB page\n"); +- kfree((void *)adev->irq.ih.ring); +- return -ENOMEM; +- } ++ memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8); + adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0; + adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1; + } +@@ -148,9 +142,9 @@ void amdgpu_ih_ring_fini(struct amdgpu_d + /* add 8 bytes for the rptr/wptr shadows and + * add them to the end of the ring allocation. + */ +- pci_unmap_single(adev->pdev, adev->irq.ih.rb_dma_addr, +- adev->irq.ih.ring_size + 8, PCI_DMA_BIDIRECTIONAL); +- kfree((void *)adev->irq.ih.ring); ++ pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8, ++ (void *)adev->irq.ih.ring, ++ adev->irq.ih.rb_dma_addr); + adev->irq.ih.ring = NULL; + } + } else { diff --git a/queue-4.2/drm-amdgpu-fix-one-warning-message.patch b/queue-4.2/drm-amdgpu-fix-one-warning-message.patch new file mode 100644 index 00000000000..2b14f15be3e --- /dev/null +++ b/queue-4.2/drm-amdgpu-fix-one-warning-message.patch @@ -0,0 +1,39 @@ +From 21df89a5667de5fcd061753d3833e7dfcf5509d3 Mon Sep 17 00:00:00 2001 +From: Jammy Zhou +Date: Fri, 7 Aug 2015 15:30:44 +0800 +Subject: drm/amdgpu: fix one warning message +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jammy Zhou + +commit 21df89a5667de5fcd061753d3833e7dfcf5509d3 upstream. + +In function 'amdgpu_uvd_cs_pass2': +warning: 'min_ctx_size' may be used uninitialized in this function + buf_sizes[0x4] = min_ctx_size; + ^ +note: 'min_ctx_size' was declared here + unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size; + ^ +Signed-off-by: Jammy Zhou +Reviewed-by: Christian König +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +@@ -374,7 +374,8 @@ static int amdgpu_uvd_cs_msg_decode(uint + unsigned height_in_mb = ALIGN(height / 16, 2); + unsigned fs_in_mb = width_in_mb * height_in_mb; + +- unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size; ++ unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; ++ unsigned min_ctx_size = 0; + + image_size = width * height; + image_size += image_size / 2; diff --git a/queue-4.2/drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch b/queue-4.2/drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch new file mode 100644 index 00000000000..bf8ba2c8785 --- /dev/null +++ b/queue-4.2/drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch @@ -0,0 +1,31 @@ +From be9fd2e978939ab3e59ee4164fa0893e70359557 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 3 Sep 2015 10:19:03 -0400 +Subject: drm/amdgpu: fix typo in dce10 watermark setup + +From: Alex Deucher + +commit be9fd2e978939ab3e59ee4164fa0893e70359557 upstream. + +Using the wrong watermwark value for the secondary +watermark. Copy paste typo. Noticed by Mykola. + +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +@@ -1331,7 +1331,7 @@ static void dce_v10_0_program_watermarks + tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); +- tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); ++ tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); + /* restore original selection */ diff --git a/queue-4.2/drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch b/queue-4.2/drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch new file mode 100644 index 00000000000..41f69fee3b4 --- /dev/null +++ b/queue-4.2/drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch @@ -0,0 +1,31 @@ +From 99a092383794e07d60644b449a01656da112eb1f Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 3 Sep 2015 10:16:23 -0400 +Subject: drm/amdgpu: fix typo in dce11 watermark setup + +From: Alex Deucher + +commit 99a092383794e07d60644b449a01656da112eb1f upstream. + +Using the wrong watermwark value for the secondary +watermark. Copy paste typo. Noticed by Mykola. + +Reviewed-by: Harry Wentland +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +@@ -1329,7 +1329,7 @@ static void dce_v11_0_program_watermarks + tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); + WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); + tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); +- tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); ++ tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); + tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); + WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); + /* restore original selection */ diff --git a/queue-4.2/drm-i915-allow-dsi-dual-link-to-be-configured-on-any-pipe.patch b/queue-4.2/drm-i915-allow-dsi-dual-link-to-be-configured-on-any-pipe.patch new file mode 100644 index 00000000000..c545c5a9017 --- /dev/null +++ b/queue-4.2/drm-i915-allow-dsi-dual-link-to-be-configured-on-any-pipe.patch @@ -0,0 +1,58 @@ +From 824257857fd81f5e749831ff9cd63566b5a86abe Mon Sep 17 00:00:00 2001 +From: Gaurav K Singh +Date: Mon, 3 Aug 2015 15:45:32 +0530 +Subject: drm/i915: Allow DSI dual link to be configured on any pipe +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Gaurav K Singh + +commit 824257857fd81f5e749831ff9cd63566b5a86abe upstream. + +Just like single link MIPI panels, similarly for dual link panels, pipe +to be configured is based on the DVO port from VBT Block 2. In hardware, +Port A is mapped with Pipe A and Port C is mapped with Pipe B. + +This issue got introduced in - + +commit 7e9804fdcffc650515c60f524b8b2076ee59e710 +Author: Jani Nikula +Date: Fri Jan 16 14:27:23 2015 +0200 + + drm/i915/dsi: add drm mipi dsi host support + +Signed-off-by: Gaurav K Singh +Reviewed-by: Ville Syrjälä +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_dsi.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_dsi.c ++++ b/drivers/gpu/drm/i915/intel_dsi.c +@@ -1036,11 +1036,7 @@ void intel_dsi_init(struct drm_device *d + intel_connector->unregister = intel_connector_unregister; + + /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ +- if (dev_priv->vbt.dsi.config->dual_link) { +- /* XXX: does dual link work on either pipe? */ +- intel_encoder->crtc_mask = (1 << PIPE_A); +- intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); +- } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { ++ if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { + intel_encoder->crtc_mask = (1 << PIPE_A); + intel_dsi->ports = (1 << PORT_A); + } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { +@@ -1048,6 +1044,9 @@ void intel_dsi_init(struct drm_device *d + intel_dsi->ports = (1 << PORT_C); + } + ++ if (dev_priv->vbt.dsi.config->dual_link) ++ intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); ++ + /* Create a DSI host (and a device) for each port. */ + for_each_dsi_port(port, intel_dsi->ports) { + struct intel_dsi_host *host; diff --git a/queue-4.2/drm-i915-always-mark-the-object-as-dirty-when-used-by-the-gpu.patch b/queue-4.2/drm-i915-always-mark-the-object-as-dirty-when-used-by-the-gpu.patch new file mode 100644 index 00000000000..7d84e07b48a --- /dev/null +++ b/queue-4.2/drm-i915-always-mark-the-object-as-dirty-when-used-by-the-gpu.patch @@ -0,0 +1,58 @@ +From 51bc140431e233284660b1d22c47dec9ecdb521e Mon Sep 17 00:00:00 2001 +From: Chris Wilson +Date: Mon, 31 Aug 2015 15:10:39 +0100 +Subject: drm/i915: Always mark the object as dirty when used by the GPU +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Chris Wilson + +commit 51bc140431e233284660b1d22c47dec9ecdb521e upstream. + +There have been many hard to track down bugs whereby userspace forgot to +flag a write buffer and then cause graphics corruption or a hung GPU +when that buffer was later purged under memory pressure (as the buffer +appeared clean, its pages would have been evicted rather than preserved +and any changes more recent than in the backing storage would be lost). +In retrospect this is a rare optimisation against memory pressure, +already the slow path. If we always mark the buffer as dirty when +accessed by the GPU, anything not used can still be evicted cheaply +(ideal behaviour for mark-and-sweep eviction) but we do not run the risk +of corruption. For correct read serialisation, userspace still has to +notify when the GPU writes to an object. However, there are certain +situations under which userspace may wish to tell white lies to the +kernel... + +Signed-off-by: Chris Wilson +Cc: Daniel Vetter +Cc: Kristian Høgsberg +Cc: Jesse Barnes +Cc: "Goel, Akash" +Cc: Michał Winiarski +Reviewed-by: Daniel Vetter +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c ++++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c +@@ -1024,6 +1024,7 @@ i915_gem_execbuffer_move_to_active(struc + u32 old_read = obj->base.read_domains; + u32 old_write = obj->base.write_domain; + ++ obj->dirty = 1; /* be paranoid */ + obj->base.write_domain = obj->base.pending_write_domain; + if (obj->base.write_domain == 0) + obj->base.pending_read_domains |= obj->base.read_domains; +@@ -1031,7 +1032,6 @@ i915_gem_execbuffer_move_to_active(struc + + i915_vma_move_to_active(vma, ring); + if (obj->base.write_domain) { +- obj->dirty = 1; + i915_gem_request_assign(&obj->last_write_req, req); + + intel_fb_obj_invalidate(obj, ring, ORIGIN_CS); diff --git a/queue-4.2/drm-i915-preserve-ssc-earlier.patch b/queue-4.2/drm-i915-preserve-ssc-earlier.patch new file mode 100644 index 00000000000..f418eebbdf8 --- /dev/null +++ b/queue-4.2/drm-i915-preserve-ssc-earlier.patch @@ -0,0 +1,117 @@ +From 69f92f67b68ab7028ffe15f0eea76b59f8859383 Mon Sep 17 00:00:00 2001 +From: Lukas Wunner +Date: Wed, 15 Jul 2015 13:57:35 +0200 +Subject: drm/i915: Preserve SSC earlier + +From: Lukas Wunner + +commit 69f92f67b68ab7028ffe15f0eea76b59f8859383 upstream. + +Commit 92122789b2d6 ("drm/i915: preserve SSC if previously set v3") +added code to intel_modeset_gem_init to override the SSC status read +from VBT with the SSC status set by BIOS. + +However, intel_modeset_gem_init is invoked *after* intel_modeset_init, +which calls intel_setup_outputs, which *modifies* SSC status by way of +intel_init_pch_refclk. So unlike advertised, intel_modeset_gem_init +doesn't preserve the SSC status set by BIOS but whatever +intel_init_pch_refclk decided on. + +This is a problem on dual gpu laptops such as the MacBook Pro which +require either a handler to switch DDC lines, or the discrete gpu +to proxy DDC/AUX communication: Both the handler and the discrete +gpu may initialize after the i915 driver, and consequently, an LVDS +connector may initially seem disconnected and the SSC therefore +is disabled by intel_init_pch_refclk, but on reprobe the connector +may turn out to be connected and the SSC must then be enabled. + +Due to 92122789b2d6 however, the SSC is not enabled on reprobe since +it is assumed BIOS disabled it while in fact it was disabled by +intel_init_pch_refclk. + +Also, because the SSC status is preserved so late, the preserved value +only ever gets used on resume but not on panel initialization: +intel_modeset_init calls intel_init_display which indirectly calls +intel_panel_use_ssc via multiple subroutines, *before* the BIOS value +overrides the VBT value in intel_modeset_gem_init (intel_panel_use_ssc +is the sole user of dev_priv->vbt.lvds_use_ssc). + +Fix this by moving the code introduced by 92122789b2d6 from +intel_modeset_gem_init to intel_modeset_init before the invocation +of intel_setup_outputs and intel_init_display. + +Add a DRM_DEBUG_KMS as suggested way back by Jani: +http://lists.freedesktop.org/archives/intel-gfx/2014-June/046666.html + +Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=88861 +Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61115 +Tested-by: Paul Hordiienko + [MBP 6,2 2010 intel ILK + nvidia GT216 pre-retina] +Tested-by: William Brown + [MBP 8,2 2011 intel SNB + amd turks pre-retina] +Tested-by: Lukas Wunner + [MBP 9,1 2012 intel IVB + nvidia GK107 pre-retina] +Tested-by: Bruno Bierbaumer + [MBP 11,3 2013 intel HSW + nvidia GK107 retina -- work in progress] +Fixes: 92122789b2d6 ("drm/i915: preserve SSC if previously set v3") +Signed-off-by: Lukas Wunner +Reviewed-by: Jesse Barnes +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++----------- + 1 file changed, 18 insertions(+), 11 deletions(-) + +--- a/drivers/gpu/drm/i915/intel_display.c ++++ b/drivers/gpu/drm/i915/intel_display.c +@@ -14665,6 +14665,24 @@ void intel_modeset_init(struct drm_devic + if (INTEL_INFO(dev)->num_pipes == 0) + return; + ++ /* ++ * There may be no VBT; and if the BIOS enabled SSC we can ++ * just keep using it to avoid unnecessary flicker. Whereas if the ++ * BIOS isn't using it, don't assume it will work even if the VBT ++ * indicates as much. ++ */ ++ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { ++ bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & ++ DREF_SSC1_ENABLE); ++ ++ if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { ++ DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", ++ bios_lvds_use_ssc ? "en" : "dis", ++ dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); ++ dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; ++ } ++ } ++ + intel_init_display(dev); + intel_init_audio(dev); + +@@ -15160,7 +15178,6 @@ void intel_modeset_setup_hw_state(struct + + void intel_modeset_gem_init(struct drm_device *dev) + { +- struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_crtc *c; + struct drm_i915_gem_object *obj; + int ret; +@@ -15169,16 +15186,6 @@ void intel_modeset_gem_init(struct drm_d + intel_init_gt_powersave(dev); + mutex_unlock(&dev->struct_mutex); + +- /* +- * There may be no VBT; and if the BIOS enabled SSC we can +- * just keep using it to avoid unnecessary flicker. Whereas if the +- * BIOS isn't using it, don't assume it will work even if the VBT +- * indicates as much. +- */ +- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) +- dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & +- DREF_SSC1_ENABLE); +- + intel_modeset_init_hw(dev); + + intel_setup_overlay(dev); diff --git a/queue-4.2/drm-qxl-validate-monitors-config-modes.patch b/queue-4.2/drm-qxl-validate-monitors-config-modes.patch new file mode 100644 index 00000000000..2ee9e873e63 --- /dev/null +++ b/queue-4.2/drm-qxl-validate-monitors-config-modes.patch @@ -0,0 +1,147 @@ +From bd3e1c7c6de9f5f70d97cdb6c817151c0477c5e3 Mon Sep 17 00:00:00 2001 +From: Jonathon Jongsma +Date: Thu, 20 Aug 2015 14:04:32 -0500 +Subject: drm/qxl: validate monitors config modes + +From: Jonathon Jongsma + +commit bd3e1c7c6de9f5f70d97cdb6c817151c0477c5e3 upstream. + +Due to some recent changes in +drm_helper_probe_single_connector_modes_merge_bits(), old custom modes +were not being pruned properly. In current kernels, +drm_mode_validate_basic() is called to sanity-check each mode in the +list. If the sanity-check passes, the mode's status gets set to to +MODE_OK. In older kernels this check was not done, so old custom modes +would still have a status of MODE_UNVERIFIED at this point, and would +therefore be pruned later in the function. + +As a result of this new behavior, the list of modes for a device always +includes every custom mode ever configured for the device, with the +largest one listed first. Since desktop environments usually choose the +first preferred mode when a hotplug event is emitted, this had the +result of making it very difficult for the user to reduce the size of +the display. + +The qxl driver did implement the mode_valid connector function, but it +was empty. In order to restore the old behavior where old custom modes +are pruned, we implement a proper mode_valid function for the qxl +driver. This function now checks each mode against the last configured +custom mode and the list of standard modes. If the mode doesn't match +any of these, its status is set to MODE_BAD so that it will be pruned as +expected. + +Signed-off-by: Jonathon Jongsma +Signed-off-by: Dave Airlie +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/qxl/qxl_display.c | 66 +++++++++++++++++++++++--------------- + drivers/gpu/drm/qxl/qxl_drv.h | 2 + + 2 files changed, 42 insertions(+), 26 deletions(-) + +--- a/drivers/gpu/drm/qxl/qxl_display.c ++++ b/drivers/gpu/drm/qxl/qxl_display.c +@@ -160,9 +160,35 @@ static int qxl_add_monitors_config_modes + *pwidth = head->width; + *pheight = head->height; + drm_mode_probed_add(connector, mode); ++ /* remember the last custom size for mode validation */ ++ qdev->monitors_config_width = mode->hdisplay; ++ qdev->monitors_config_height = mode->vdisplay; + return 1; + } + ++static struct mode_size { ++ int w; ++ int h; ++} common_modes[] = { ++ { 640, 480}, ++ { 720, 480}, ++ { 800, 600}, ++ { 848, 480}, ++ {1024, 768}, ++ {1152, 768}, ++ {1280, 720}, ++ {1280, 800}, ++ {1280, 854}, ++ {1280, 960}, ++ {1280, 1024}, ++ {1440, 900}, ++ {1400, 1050}, ++ {1680, 1050}, ++ {1600, 1200}, ++ {1920, 1080}, ++ {1920, 1200} ++}; ++ + static int qxl_add_common_modes(struct drm_connector *connector, + unsigned pwidth, + unsigned pheight) +@@ -170,29 +196,6 @@ static int qxl_add_common_modes(struct d + struct drm_device *dev = connector->dev; + struct drm_display_mode *mode = NULL; + int i; +- struct mode_size { +- int w; +- int h; +- } common_modes[] = { +- { 640, 480}, +- { 720, 480}, +- { 800, 600}, +- { 848, 480}, +- {1024, 768}, +- {1152, 768}, +- {1280, 720}, +- {1280, 800}, +- {1280, 854}, +- {1280, 960}, +- {1280, 1024}, +- {1440, 900}, +- {1400, 1050}, +- {1680, 1050}, +- {1600, 1200}, +- {1920, 1080}, +- {1920, 1200} +- }; +- + for (i = 0; i < ARRAY_SIZE(common_modes); i++) { + mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, + 60, false, false, false); +@@ -823,11 +826,22 @@ static int qxl_conn_get_modes(struct drm + static int qxl_conn_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) + { ++ struct drm_device *ddev = connector->dev; ++ struct qxl_device *qdev = ddev->dev_private; ++ int i; ++ + /* TODO: is this called for user defined modes? (xrandr --add-mode) + * TODO: check that the mode fits in the framebuffer */ +- DRM_DEBUG("%s: %dx%d status=%d\n", mode->name, mode->hdisplay, +- mode->vdisplay, mode->status); +- return MODE_OK; ++ ++ if(qdev->monitors_config_width == mode->hdisplay && ++ qdev->monitors_config_height == mode->vdisplay) ++ return MODE_OK; ++ ++ for (i = 0; i < ARRAY_SIZE(common_modes); i++) { ++ if (common_modes[i].w == mode->hdisplay && common_modes[i].h == mode->vdisplay) ++ return MODE_OK; ++ } ++ return MODE_BAD; + } + + static struct drm_encoder *qxl_best_encoder(struct drm_connector *connector) +--- a/drivers/gpu/drm/qxl/qxl_drv.h ++++ b/drivers/gpu/drm/qxl/qxl_drv.h +@@ -325,6 +325,8 @@ struct qxl_device { + struct work_struct fb_work; + + struct drm_property *hotplug_mode_update_property; ++ int monitors_config_width; ++ int monitors_config_height; + }; + + /* forward declaration for QXL_INFO_IO */ diff --git a/queue-4.2/drm-radeon-atom-send-out-the-full-aux-address.patch b/queue-4.2/drm-radeon-atom-send-out-the-full-aux-address.patch new file mode 100644 index 00000000000..7c961fcbe5e --- /dev/null +++ b/queue-4.2/drm-radeon-atom-send-out-the-full-aux-address.patch @@ -0,0 +1,39 @@ +From 3f8340cc72c9a1a4b49bce7802afd7f248400ef5 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= +Date: Thu, 27 Aug 2015 17:23:31 +0300 +Subject: drm/radeon/atom: Send out the full AUX address +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= + +commit 3f8340cc72c9a1a4b49bce7802afd7f248400ef5 upstream. + +AUX addresses are 20 bits long. Send out the entire address instead of +just the low 16 bits. + +Cc: Alex Deucher +Cc: "Christian König" +Signed-off-by: Ville Syrjälä +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/atombios_dp.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/atombios_dp.c ++++ b/drivers/gpu/drm/radeon/atombios_dp.c +@@ -171,8 +171,9 @@ radeon_dp_aux_transfer_atom(struct drm_d + return -E2BIG; + + tx_buf[0] = msg->address & 0xff; +- tx_buf[1] = msg->address >> 8; +- tx_buf[2] = msg->request << 4; ++ tx_buf[1] = (msg->address >> 8) & 0xff; ++ tx_buf[2] = (msg->request << 4) | ++ ((msg->address >> 16) & 0xf); + tx_buf[3] = msg->size ? (msg->size - 1) : 0; + + switch (msg->request & ~DP_AUX_I2C_MOT) { diff --git a/queue-4.2/drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch b/queue-4.2/drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch new file mode 100644 index 00000000000..90a2ec0cc87 --- /dev/null +++ b/queue-4.2/drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch @@ -0,0 +1,47 @@ +From 86b7709d48f0df8796bddd7e1ce45c6fb7a7c6ec Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Thu, 27 Aug 2015 09:52:22 -0400 +Subject: drm/radeon: fix HDMI quantization_range for pre-DCE5 asics + +From: Alex Deucher + +commit 86b7709d48f0df8796bddd7e1ce45c6fb7a7c6ec upstream. + +Support for output_csc is only available on DCE5 and newer so +don't mess with the HDMI quantization_range on pre-DCE5 asics. + +bug: +https://bugs.freedesktop.org/show_bug.cgi?id=83226 + +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_audio.c | 16 +++++++++------- + 1 file changed, 9 insertions(+), 7 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_audio.c ++++ b/drivers/gpu/drm/radeon/radeon_audio.c +@@ -522,13 +522,15 @@ static int radeon_audio_set_avi_packet(s + return err; + } + +- if (drm_rgb_quant_range_selectable(radeon_connector_edid(connector))) { +- if (radeon_encoder->output_csc == RADEON_OUTPUT_CSC_TVRGB) +- frame.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; +- else +- frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; +- } else { +- frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; ++ if (radeon_encoder->output_csc != RADEON_OUTPUT_CSC_BYPASS) { ++ if (drm_rgb_quant_range_selectable(radeon_connector_edid(connector))) { ++ if (radeon_encoder->output_csc == RADEON_OUTPUT_CSC_TVRGB) ++ frame.quantization_range = HDMI_QUANTIZATION_RANGE_LIMITED; ++ else ++ frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; ++ } else { ++ frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; ++ } + } + + err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); diff --git a/queue-4.2/drm-radeon-native-send-out-the-full-aux-address.patch b/queue-4.2/drm-radeon-native-send-out-the-full-aux-address.patch new file mode 100644 index 00000000000..d89b354af26 --- /dev/null +++ b/queue-4.2/drm-radeon-native-send-out-the-full-aux-address.patch @@ -0,0 +1,40 @@ +From 7040c399aea2b0213a9aefd73e507369a6d641d6 Mon Sep 17 00:00:00 2001 +From: Alex Deucher +Date: Mon, 31 Aug 2015 11:15:05 -0400 +Subject: drm/radeon/native: Send out the full AUX address +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher + +commit 7040c399aea2b0213a9aefd73e507369a6d641d6 upstream. + +AUX addresses are 20 bits long. Send out the entire address instead of +just the low 16 bits. + +Port of: +drm/radeon/atom: Send out the full AUX address +to radeon non-atom aux path + +Reviewed-by: Christian König +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/radeon_dp_auxch.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_dp_auxch.c ++++ b/drivers/gpu/drm/radeon/radeon_dp_auxch.c +@@ -116,8 +116,8 @@ radeon_dp_aux_transfer_native(struct drm + AUX_SW_WR_BYTES(bytes)); + + /* write the data header into the registers */ +- /* request, addres, msg size */ +- byte = (msg->request << 4); ++ /* request, address, msg size */ ++ byte = (msg->request << 4) | ((msg->address >> 16) & 0xf); + WREG32(AUX_SW_DATA + aux_offset[instance], + AUX_SW_DATA_MASK(byte) | AUX_SW_AUTOINCREMENT_DISABLE); + diff --git a/queue-4.2/series b/queue-4.2/series index bb1035221b8..0c7460d6954 100644 --- a/queue-4.2/series +++ b/queue-4.2/series @@ -1,3 +1,16 @@ drm-radeon-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch drm-i915-apply-the-pci_d0-d3-hibernation-workaround-everywhere-on-pre-gen6.patch drm-i915-check-dp-link-status-on-long-hpd-too.patch +drm-radeon-atom-send-out-the-full-aux-address.patch +drm-amdgpu-atom-send-out-the-full-aux-address.patch +drm-radeon-native-send-out-the-full-aux-address.patch +drm-radeon-fix-hdmi-quantization_range-for-pre-dce5-asics.patch +drm-amdgpu-fix-one-warning-message.patch +drm-amdgpu-don-t-link-train-displayport-on-hpd-until-we-get-the-dpcd.patch +drm-amdgpu-fix-ih-ring-allocation-for-bus-addresses-v2.patch +drm-amdgpu-fix-typo-in-dce11-watermark-setup.patch +drm-amdgpu-fix-typo-in-dce10-watermark-setup.patch +drm-i915-preserve-ssc-earlier.patch +drm-qxl-validate-monitors-config-modes.patch +drm-i915-allow-dsi-dual-link-to-be-configured-on-any-pipe.patch +drm-i915-always-mark-the-object-as-dirty-when-used-by-the-gpu.patch -- 2.47.2