From 77700bcc1dc50651567e0835dbcf1710cdb108fc Mon Sep 17 00:00:00 2001 From: Shmuel Leib Melamud Date: Wed, 11 Jun 2025 03:25:51 +0300 Subject: [PATCH] clk: renesas: Handle CLK_TYPE_GEN4_MDSEL in gen3_clk_get_rate64() Add support of CLK_TYPE_GEN4_MDSEL clock type to gen3_clk_get_rate64() function. In particular, this type of clock is used by Renesas R-Car Gen4 watchdog. It operates similarly to CLK_TYPE_GEN3_MDSEL clock. Signed-off-by: Shmuel Leib Melamud Reviewed-by: Mattijs Korpershoek Reviewed-by: Marek Vasut Reviewed-by: Stefan Roese --- drivers/clk/renesas/clk-rcar-gen3.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c index 375cc4a4930..5745acf4023 100644 --- a/drivers/clk/renesas/clk-rcar-gen3.c +++ b/drivers/clk/renesas/clk-rcar-gen3.c @@ -68,7 +68,7 @@ static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk, if (ret) return ret; - if (core->type == CLK_TYPE_GEN3_MDSEL) { + if (core->type == CLK_TYPE_GEN3_MDSEL || core->type == CLK_TYPE_GEN4_MDSEL) { shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16; parent->dev = clk->dev; parent->id = core->parent >> shift; @@ -318,6 +318,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk) "FIXED"); case CLK_TYPE_GEN3_MDSEL: + fallthrough; + case CLK_TYPE_GEN4_MDSEL: shift = priv->cpg_mode & BIT(core->offset) ? 0 : 16; div = (core->div >> shift) & 0xffff; rate = gen3_clk_get_rate64(&parent) / div; -- 2.47.2