From 77eb0085c8fe48e77f845d9db0d3c4c4ccf7c4f1 Mon Sep 17 00:00:00 2001 From: Anton Kochkov Date: Thu, 12 Jan 2023 14:24:02 +0000 Subject: [PATCH] target/tricore: Fix OPC1_16_SRO_LD_H translation MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bastian Koppelmann Signed-off-by: Eitan Eliahu Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652 Message-Id: <20230112142258.514079-1-anton.kochkov@proton.me> Signed-off-by: Bastian Koppelmann --- target/tricore/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/tricore/translate.c b/target/tricore/translate.c index ab386cef50f..7ac34efd765 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -3878,7 +3878,7 @@ static void decode_sro_opc(DisasContext *ctx, int op1) gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB); break; case OPC1_16_SRO_LD_H: - gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW); + gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW); break; case OPC1_16_SRO_LD_W: gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL); -- 2.39.5