From 791651e39076e42e7de6f47fac4a885a075e4e13 Mon Sep 17 00:00:00 2001
From: Patrice Chotard <patrice.chotard@st.com>
Date: Tue, 12 Dec 2017 09:49:33 +0100
Subject: [PATCH] ARM: DTS: stm32: add stm32f429-disco-u-boot dts file

_ Add gpio compatible and aliases for stm32f429

_ Add FMC sdram node with associated new bindings value to
  manage second bank (ie bank 1).

_ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
  pwrcfg and gpio nodes.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
 arch/arm/dts/stm32f429-disco-u-boot.dtsi | 204 +++++++++++++++++++++++
 include/dt-bindings/memory/stm32-sdram.h |   2 +
 2 files changed, 206 insertions(+)
 create mode 100644 arch/arm/dts/stm32f429-disco-u-boot.dtsi

diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
new file mode 100644
index 0000000000..59dda436b4
--- /dev/null
+++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi
@@ -0,0 +1,204 @@
+/*
+ * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
+ * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/memory/stm32-sdram.h>
+/{
+	clocks {
+		u-boot,dm-pre-reloc;
+	};
+
+	aliases {
+		/* Aliases for gpios so as to use sequence */
+		gpio0 = &gpioa;
+		gpio1 = &gpiob;
+		gpio2 = &gpioc;
+		gpio3 = &gpiod;
+		gpio4 = &gpioe;
+		gpio5 = &gpiof;
+		gpio6 = &gpiog;
+		gpio7 = &gpioh;
+		gpio8 = &gpioi;
+		gpio9 = &gpioj;
+		gpio10 = &gpiok;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+		pin-controller {
+			u-boot,dm-pre-reloc;
+		};
+
+		fmc: fmc@A0000000 {
+			compatible = "st,stm32-fmc";
+			reg = <0xA0000000 0x1000>;
+			clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
+			pinctrl-0 = <&fmc_pins>;
+			pinctrl-names = "default";
+			u-boot,dm-pre-reloc;
+
+			/*
+			 * Memory configuration from sdram datasheet
+			 * IS42S16400J
+			 */
+			bank1: bank@1 {
+			       st,sdram-control = /bits/ 8 <NO_COL_8
+							    NO_ROW_12
+							    MWIDTH_16
+							    BANKS_4
+							    CAS_3
+							    SDCLK_2
+							    RD_BURST_EN
+							    RD_PIPE_DL_0>;
+			       st,sdram-timing = /bits/ 8 <TMRD_3
+							   TXSR_7
+							   TRAS_4
+							   TRC_6
+							   TWR_2
+							   TRP_2 TRCD_2>;
+			       st,sdram-refcount = < 1386 >;
+		       };
+		};
+	};
+};
+
+&clk_hse {
+	u-boot,dm-pre-reloc;
+};
+
+&clk_lse {
+	u-boot,dm-pre-reloc;
+};
+
+&clk_i2s_ckin {
+	u-boot,dm-pre-reloc;
+};
+
+&pwrcfg {
+	u-boot,dm-pre-reloc;
+};
+
+&rcc {
+	u-boot,dm-pre-reloc;
+};
+
+&gpioa {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiob {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioc {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiod {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioe {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiof {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiog {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioh {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioi {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpioj {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&gpiok {
+	compatible = "st,stm32-gpio";
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	usart1_pins_a: usart1@0	{
+		u-boot,dm-pre-reloc;
+		pins1 {
+			u-boot,dm-pre-reloc;
+		};
+		pins2 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	fmc_pins: fmc@0 {
+		u-boot,dm-pre-reloc;
+		pins
+		{
+			pinmux = <STM32_PINMUX('D',10, AF12)>, /* D15 */
+				 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
+				 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
+				 <STM32_PINMUX('E',15, AF12)>, /* D12 */
+				 <STM32_PINMUX('E',14, AF12)>, /* D11 */
+				 <STM32_PINMUX('E',13, AF12)>, /* D10 */
+				 <STM32_PINMUX('E',12, AF12)>, /* D09 */
+				 <STM32_PINMUX('E',11, AF12)>, /* D08 */
+				 <STM32_PINMUX('E',10, AF12)>, /* D07 */
+				 <STM32_PINMUX('E', 9, AF12)>, /* D06 */
+				 <STM32_PINMUX('E', 8, AF12)>, /* D05 */
+				 <STM32_PINMUX('E', 7, AF12)>, /* D04 */
+				 <STM32_PINMUX('D', 1, AF12)>, /* D03 */
+				 <STM32_PINMUX('D', 0, AF12)>, /* D02 */
+				 <STM32_PINMUX('D',15, AF12)>, /* D01 */
+				 <STM32_PINMUX('D',14, AF12)>, /* D00 */
+
+				 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
+				 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
+
+				 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
+				 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
+
+				 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
+				 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
+				 <STM32_PINMUX('F',15, AF12)>, /* A09 */
+				 <STM32_PINMUX('F',14, AF12)>, /* A08 */
+				 <STM32_PINMUX('F',13, AF12)>, /* A07 */
+				 <STM32_PINMUX('F',12, AF12)>, /* A06 */
+				 <STM32_PINMUX('F', 5, AF12)>, /* A05 */
+				 <STM32_PINMUX('F', 4, AF12)>, /* A04 */
+				 <STM32_PINMUX('F', 3, AF12)>, /* A03 */
+				 <STM32_PINMUX('F', 2, AF12)>, /* A02 */
+				 <STM32_PINMUX('F', 1, AF12)>, /* A01 */
+				 <STM32_PINMUX('F', 0, AF12)>, /* A00 */
+
+				 <STM32_PINMUX('B', 6, AF12)>, /* SDNE1 */
+				 <STM32_PINMUX('C', 0, AF12)>, /* SDNWE */
+				 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
+				 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
+				 <STM32_PINMUX('B', 5, AF12)>, /* SDCKE1 */
+				 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
+			slew-rate = <2>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/include/dt-bindings/memory/stm32-sdram.h b/include/dt-bindings/memory/stm32-sdram.h
index c2b911febf..ab91d2b7f6 100644
--- a/include/dt-bindings/memory/stm32-sdram.h
+++ b/include/dt-bindings/memory/stm32-sdram.h
@@ -30,8 +30,10 @@
 /* Timing = value +1 cycles */
 #define TMRD_1		(1 - 1)
 #define TMRD_2		(2 - 1)
+#define TMRD_3		(3 - 1)
 #define TXSR_1		(1 - 1)
 #define TXSR_6		(6 - 1)
+#define TXSR_7		(7 - 1)
 #define TRAS_1		(1 - 1)
 #define TRAS_4		(4 - 1)
 #define TRC_6		(6 - 1)
-- 
2.39.5