From 7a3014a9a26b61b1df246426b6510b8956acfaab Mon Sep 17 00:00:00 2001 From: =?utf8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Tue, 19 Dec 2023 17:57:49 +0000 Subject: [PATCH] target/arm: Restrict DC CVAP & DC CVADP instructions to TCG accel MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Hardware accelerators handle that in *hardware*. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20231130142519.28417-3-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5d4796b99a8..436a43a4b7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7649,6 +7649,7 @@ static const ARMCPRegInfo rndr_reginfo[] = { static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t value) { +#ifdef CONFIG_TCG ARMCPU *cpu = env_archcpu(env); /* CTR_EL0 System register -> DminLine, bits [19:16] */ uint64_t dline_size = 4 << ((cpu->ctr >> 16) & 0xF); @@ -7673,6 +7674,10 @@ static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, } #endif /*CONFIG_USER_ONLY*/ } +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } static const ARMCPRegInfo dcpop_reg[] = { -- 2.39.5