From 7df005c4c6fa0300f7bfe54e184bc5291bb742af Mon Sep 17 00:00:00 2001 From: Michael Brown Date: Mon, 2 Jun 2025 08:36:22 +0100 Subject: [PATCH] [riscv] Add fences around early UART writes Add a fence between the write to the UART transmit register and the subsequent read from the transmit status register, to ensure that the status correctly reflects the occurrence of the write. Signed-off-by: Michael Brown --- src/arch/riscv/prefix/libprefix.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/arch/riscv/prefix/libprefix.S b/src/arch/riscv/prefix/libprefix.S index 583f27117..3fe01d7c8 100644 --- a/src/arch/riscv/prefix/libprefix.S +++ b/src/arch/riscv/prefix/libprefix.S @@ -204,6 +204,7 @@ early_uart_reg_base_64_done_\@: .macro print_char_uart_8250 early_uart_reg_base a7 sb a0, EARLY_UART_8250_TX(a7) + fence early_uart_8250_wait_\@: lbu a1, EARLY_UART_8250_LSR(a7) andi a1, a1, EARLY_UART_8250_LSR_THRE @@ -236,6 +237,7 @@ early_uart_8250_wait_\@: .macro print_char_uart_sifive early_uart_reg_base a7 sw a0, EARLY_UART_SIFIVE_TXFIFO(a7) + fence early_uart_sifive_wait_\@: lw a1, EARLY_UART_SIFIVE_TXFIFO(a7) bltz a1, early_uart_sifive_wait_\@ -- 2.47.3