From 7fb4a323f188ecaa22a823b22e5f39f049e70bc3 Mon Sep 17 00:00:00 2001
From: daichengrong <daichengrong@iscas.ac.cn>
Date: Tue, 18 Feb 2025 16:19:01 +0800
Subject: [PATCH] riscv: add dl_hwcap for capability detection

Availability of ZVK* should be determined with dl_hwcap and hwcap.

Reviewed-by: Paul Dale <ppzgs1@gmail.com>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/26811)
---
 crypto/riscvcap.c           | 13 ++++++++++---
 include/crypto/riscv_arch.h |  6 ++++++
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/crypto/riscvcap.c b/crypto/riscvcap.c
index b87fe4c94e2..01bbb9df43d 100644
--- a/crypto/riscvcap.c
+++ b/crypto/riscvcap.c
@@ -21,6 +21,7 @@
 # include <unistd.h>
 # include <sys/syscall.h>
 # include <asm/hwprobe.h>
+# include <sys/auxv.h>
 #endif
 
 extern size_t riscv_vlen_asm(void);
@@ -30,6 +31,10 @@ static void strtoupper(char *str);
 
 static size_t vlen = 0;
 
+#ifdef OSSL_RISCV_HWPROBE
+unsigned int OPENSSL_riscv_hwcap_P = 0;
+#endif
+
 uint32_t OPENSSL_rdtsc(void)
 {
     return 0;
@@ -100,9 +105,10 @@ static void hwprobe_to_cap(void)
                 if (pairs[j].key == RISCV_capabilities[i].hwprobe_key
                         && (pairs[j].value & RISCV_capabilities[i].hwprobe_value)
                            != 0)
-                    /* Match, set relevant bit in OPENSSL_riscvcap_P[] */
-                    OPENSSL_riscvcap_P[RISCV_capabilities[i].index] |=
-                        (1 << RISCV_capabilities[i].bit_offset);
+                    if (!IS_IN_DEPEND_VECTOR(RISCV_capabilities[i].bit_offset) || VECTOR_CAPABLE)
+                        /* Match, set relevant bit in OPENSSL_riscvcap_P[] */
+                        OPENSSL_riscvcap_P[RISCV_capabilities[i].index] |=
+                            (1 << RISCV_capabilities[i].bit_offset);
             }
         }
     }
@@ -131,6 +137,7 @@ void OPENSSL_cpuid_setup(void)
     }
 #ifdef OSSL_RISCV_HWPROBE
     else {
+        OPENSSL_riscv_hwcap_P = getauxval(AT_HWCAP);
         hwprobe_to_cap();
     }
 #endif
diff --git a/include/crypto/riscv_arch.h b/include/crypto/riscv_arch.h
index 885842763d9..0cd4c7315f6 100644
--- a/include/crypto/riscv_arch.h
+++ b/include/crypto/riscv_arch.h
@@ -22,6 +22,12 @@
      */
 #   ifdef __NR_riscv_hwprobe
 #    define OSSL_RISCV_HWPROBE
+#    include <asm/hwcap.h>
+extern unsigned int OPENSSL_riscv_hwcap_P;
+#    define VECTOR_CAPABLE (OPENSSL_riscv_hwcap_P & COMPAT_HWCAP_ISA_V)
+#    define ZVX_MIN 15
+#    define ZVX_MAX 23
+#    define IS_IN_DEPEND_VECTOR(offset) ((ZVX_MIN >= offset) && (offset <= ZVX_MAX))
 #   endif
 #  endif
 # endif
-- 
2.47.2