From 8614dcc300bd6d57a926950d8d47aeb4cf8abf5f Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 29 Apr 2014 16:44:46 -0700 Subject: [PATCH] 3.10-stable patches added patches: arm64-do-not-synchronise-i-and-d-caches-for-special-ptes.patch arm64-make-dma-coherent-and-strongly-ordered-mappings-not-executable.patch arm-7728-1-mm-use-phys_addr_t-properly-for-ioremap-functions.patch arm-7954-1-mm-remove-remaining-domain-support-from-armv6.patch arm-8007-1-remove-extraneous-kcmp-syscall-ignore.patch arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch arm-dts-keep-g3d-regulator-always-on-for-exynos5250-arndale.patch arm-mvebu-ensure-the-mdio-node-has-a-clock-reference-on-armada-370-xp.patch arm-omap2-intc-acknowledge-stuck-active-interrupts.patch arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch arm-omap4-fix-definition-of-is_pm44xx_erratum.patch arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch asoc-cs42l51-fix-soc_double_r_sx_tlv-shift-values-for-adc-pcm-and-analog-kcontrols.patch asoc-cs42l52-fix-mask-bits-for-soc_value_enum_single.patch asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch --- ...ddr_t-properly-for-ioremap-functions.patch | 184 +++++++++++++++++ ...-remaining-domain-support-from-armv6.patch | 193 ++++++++++++++++++ ...emove-extraneous-kcmp-syscall-ignore.patch | 31 +++ ...fix-do_div-bug-in-big-endian-systems.patch | 45 ++++ ...kdump-add-arch_crash_save_vmcoreinfo.patch | 38 ++++ ...tor-always-on-for-exynos5250-arndale.patch | 44 ++++ ...s-a-clock-reference-on-armada-370-xp.patch | 37 ++++ ...-acknowledge-stuck-active-interrupts.patch | 57 ++++++ ...orrect-clock-domains-for-usb-modules.patch | 49 +++++ ...-fix-definition-of-is_pm44xx_erratum.patch | 38 ++++ ...clude-irqs.h-for-pxa_nr_builtin_gpio.patch | 37 ++++ ...nise-i-and-d-caches-for-special-ptes.patch | 34 +++ ...ngly-ordered-mappings-not-executable.patch | 40 ++++ ...ues-for-adc-pcm-and-analog-kcontrols.patch | 54 +++++ ...-mask-bits-for-soc_value_enum_single.patch | 58 ++++++ ...-mask-bits-for-soc_value_enum_single.patch | 49 +++++ queue-3.10/series | 16 ++ queue-3.14/series | 21 ++ queue-3.4/series | 6 + 19 files changed, 1031 insertions(+) create mode 100644 queue-3.10/arm-7728-1-mm-use-phys_addr_t-properly-for-ioremap-functions.patch create mode 100644 queue-3.10/arm-7954-1-mm-remove-remaining-domain-support-from-armv6.patch create mode 100644 queue-3.10/arm-8007-1-remove-extraneous-kcmp-syscall-ignore.patch create mode 100644 queue-3.10/arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch create mode 100644 queue-3.10/arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch create mode 100644 queue-3.10/arm-dts-keep-g3d-regulator-always-on-for-exynos5250-arndale.patch create mode 100644 queue-3.10/arm-mvebu-ensure-the-mdio-node-has-a-clock-reference-on-armada-370-xp.patch create mode 100644 queue-3.10/arm-omap2-intc-acknowledge-stuck-active-interrupts.patch create mode 100644 queue-3.10/arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch create mode 100644 queue-3.10/arm-omap4-fix-definition-of-is_pm44xx_erratum.patch create mode 100644 queue-3.10/arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch create mode 100644 queue-3.10/arm64-do-not-synchronise-i-and-d-caches-for-special-ptes.patch create mode 100644 queue-3.10/arm64-make-dma-coherent-and-strongly-ordered-mappings-not-executable.patch create mode 100644 queue-3.10/asoc-cs42l51-fix-soc_double_r_sx_tlv-shift-values-for-adc-pcm-and-analog-kcontrols.patch create mode 100644 queue-3.10/asoc-cs42l52-fix-mask-bits-for-soc_value_enum_single.patch create mode 100644 queue-3.10/asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch create mode 100644 queue-3.10/series create mode 100644 queue-3.14/series create mode 100644 queue-3.4/series diff --git a/queue-3.10/arm-7728-1-mm-use-phys_addr_t-properly-for-ioremap-functions.patch b/queue-3.10/arm-7728-1-mm-use-phys_addr_t-properly-for-ioremap-functions.patch new file mode 100644 index 00000000000..2334ef9b220 --- /dev/null +++ b/queue-3.10/arm-7728-1-mm-use-phys_addr_t-properly-for-ioremap-functions.patch @@ -0,0 +1,184 @@ +From 9b97173e785a54c5df0aa23d1e1f680f61e36e43 Mon Sep 17 00:00:00 2001 +From: Laura Abbott +Date: Thu, 16 May 2013 19:40:22 +0100 +Subject: ARM: 7728/1: mm: Use phys_addr_t properly for ioremap functions + +From: Laura Abbott + +commit 9b97173e785a54c5df0aa23d1e1f680f61e36e43 upstream. + +Several of the ioremap functions use unsigned long in places +resulting in truncation if physical addresses greater than +4G are passed in. Change the types of the functions and the +callers accordingly. + +Cc: Krzysztof Halasa +Cc: Arnd Bergmann +Cc: Stephen Boyd +Signed-off-by: Laura Abbott +Signed-off-by: Russell King +Cc: Wang Nan +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/io.h | 8 ++++---- + arch/arm/mach-ebsa110/core.c | 2 +- + arch/arm/mach-imx/mm-imx3.c | 2 +- + arch/arm/mach-iop13xx/io.c | 2 +- + arch/arm/mach-ixp4xx/common.c | 2 +- + arch/arm/mach-msm/common.h | 2 +- + arch/arm/mach-msm/io.c | 2 +- + arch/arm/mm/ioremap.c | 10 +++++----- + arch/arm/mm/nommu.c | 6 +++--- + 9 files changed, 18 insertions(+), 18 deletions(-) + +--- a/arch/arm/include/asm/io.h ++++ b/arch/arm/include/asm/io.h +@@ -130,16 +130,16 @@ static inline u32 __raw_readl(const vola + */ + extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long, + size_t, unsigned int, void *); +-extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int, ++extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int, + void *); + + extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int); +-extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int); +-extern void __iomem *__arm_ioremap_exec(unsigned long, size_t, bool cached); ++extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int); ++extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached); + extern void __iounmap(volatile void __iomem *addr); + extern void __arm_iounmap(volatile void __iomem *addr); + +-extern void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, ++extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, + unsigned int, void *); + extern void (*arch_iounmap)(volatile void __iomem *); + +--- a/arch/arm/mach-ebsa110/core.c ++++ b/arch/arm/mach-ebsa110/core.c +@@ -116,7 +116,7 @@ static void __init ebsa110_map_io(void) + iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc)); + } + +-static void __iomem *ebsa110_ioremap_caller(unsigned long cookie, size_t size, ++static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size, + unsigned int flags, void *caller) + { + return (void __iomem *)cookie; +--- a/arch/arm/mach-imx/mm-imx3.c ++++ b/arch/arm/mach-imx/mm-imx3.c +@@ -65,7 +65,7 @@ static void imx3_idle(void) + : "=r" (reg)); + } + +-static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size, ++static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size, + unsigned int mtype, void *caller) + { + if (mtype == MT_DEVICE) { +--- a/arch/arm/mach-iop13xx/io.c ++++ b/arch/arm/mach-iop13xx/io.c +@@ -23,7 +23,7 @@ + + #include "pci.h" + +-static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie, ++static void __iomem *__iop13xx_ioremap_caller(phys_addr_t cookie, + size_t size, unsigned int mtype, void *caller) + { + void __iomem * retval; +--- a/arch/arm/mach-ixp4xx/common.c ++++ b/arch/arm/mach-ixp4xx/common.c +@@ -559,7 +559,7 @@ void ixp4xx_restart(char mode, const cha + * fallback to the default. + */ + +-static void __iomem *ixp4xx_ioremap_caller(unsigned long addr, size_t size, ++static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size, + unsigned int mtype, void *caller) + { + if (!is_pci_memory(addr)) +--- a/arch/arm/mach-msm/common.h ++++ b/arch/arm/mach-msm/common.h +@@ -23,7 +23,7 @@ extern void msm_map_msm8x60_io(void); + extern void msm_map_msm8960_io(void); + extern void msm_map_qsd8x50_io(void); + +-extern void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, ++extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, + unsigned int mtype, void *caller); + + extern struct smp_operations msm_smp_ops; +--- a/arch/arm/mach-msm/io.c ++++ b/arch/arm/mach-msm/io.c +@@ -172,7 +172,7 @@ void __init msm_map_msm7x30_io(void) + } + #endif /* CONFIG_ARCH_MSM7X30 */ + +-void __iomem *__msm_ioremap_caller(unsigned long phys_addr, size_t size, ++void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, + unsigned int mtype, void *caller) + { + if (mtype == MT_DEVICE) { +--- a/arch/arm/mm/ioremap.c ++++ b/arch/arm/mm/ioremap.c +@@ -331,10 +331,10 @@ void __iomem * __arm_ioremap_pfn_caller( + return (void __iomem *) (offset + addr); + } + +-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size, ++void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size, + unsigned int mtype, void *caller) + { +- unsigned long last_addr; ++ phys_addr_t last_addr; + unsigned long offset = phys_addr & ~PAGE_MASK; + unsigned long pfn = __phys_to_pfn(phys_addr); + +@@ -367,12 +367,12 @@ __arm_ioremap_pfn(unsigned long pfn, uns + } + EXPORT_SYMBOL(__arm_ioremap_pfn); + +-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, ++void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, + unsigned int, void *) = + __arm_ioremap_caller; + + void __iomem * +-__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) ++__arm_ioremap(phys_addr_t phys_addr, size_t size, unsigned int mtype) + { + return arch_ioremap_caller(phys_addr, size, mtype, + __builtin_return_address(0)); +@@ -387,7 +387,7 @@ EXPORT_SYMBOL(__arm_ioremap); + * CONFIG_GENERIC_ALLOCATOR for allocating external memory. + */ + void __iomem * +-__arm_ioremap_exec(unsigned long phys_addr, size_t size, bool cached) ++__arm_ioremap_exec(phys_addr_t phys_addr, size_t size, bool cached) + { + unsigned int mtype; + +--- a/arch/arm/mm/nommu.c ++++ b/arch/arm/mm/nommu.c +@@ -87,16 +87,16 @@ void __iomem *__arm_ioremap_pfn_caller(u + return __arm_ioremap_pfn(pfn, offset, size, mtype); + } + +-void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size, ++void __iomem *__arm_ioremap(phys_addr_t phys_addr, size_t size, + unsigned int mtype) + { + return (void __iomem *)phys_addr; + } + EXPORT_SYMBOL(__arm_ioremap); + +-void __iomem * (*arch_ioremap_caller)(unsigned long, size_t, unsigned int, void *); ++void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t, unsigned int, void *); + +-void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size, ++void __iomem *__arm_ioremap_caller(phys_addr_t phys_addr, size_t size, + unsigned int mtype, void *caller) + { + return __arm_ioremap(phys_addr, size, mtype); diff --git a/queue-3.10/arm-7954-1-mm-remove-remaining-domain-support-from-armv6.patch b/queue-3.10/arm-7954-1-mm-remove-remaining-domain-support-from-armv6.patch new file mode 100644 index 00000000000..7b21e1b4f6c --- /dev/null +++ b/queue-3.10/arm-7954-1-mm-remove-remaining-domain-support-from-armv6.patch @@ -0,0 +1,193 @@ +From b6ccb9803e90c16b212cf4ed62913a7591e79a39 Mon Sep 17 00:00:00 2001 +From: Will Deacon +Date: Fri, 7 Feb 2014 19:12:27 +0100 +Subject: ARM: 7954/1: mm: remove remaining domain support from ARMv6 + +From: Will Deacon + +commit b6ccb9803e90c16b212cf4ed62913a7591e79a39 upstream. + +CPU_32v6 currently selects CPU_USE_DOMAINS if CPU_V6 and MMU. This is +because ARM 1136 r0pX CPUs lack the v6k extensions, and therefore do +not have hardware thread registers. The lack of these registers requires +the kernel to update the vectors page at each context switch in order to +write a new TLS pointer. This write must be done via the userspace +mapping, since aliasing caches can lead to expensive flushing when using +kmap. Finally, this requires the vectors page to be mapped r/w for +kernel and r/o for user, which has implications for things like put_user +which must trigger CoW appropriately when targetting user pages. + +The upshot of all this is that a v6/v7 kernel makes use of domains to +segregate kernel and user memory accesses. This has the nasty +side-effect of making device mappings executable, which has been +observed to cause subtle bugs on recent cores (e.g. Cortex-A15 +performing a speculative instruction fetch from the GIC and acking an +interrupt in the process). + +This patch solves this problem by removing the remaining domain support +from ARMv6. A new memory type is added specifically for the vectors page +which allows that page (and only that page) to be mapped as user r/o, +kernel r/w. All other user r/o pages are mapped also as kernel r/o. +Patch co-developed with Russell King. + +Signed-off-by: Will Deacon +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/futex.h | 6 ------ + arch/arm/include/asm/pgtable-2level.h | 1 + + arch/arm/mm/Kconfig | 3 +-- + arch/arm/mm/mmu.c | 10 ++++++++++ + arch/arm/mm/proc-macros.S | 19 ++++++------------- + arch/arm/mm/proc-v7-2level.S | 7 ------- + 6 files changed, 18 insertions(+), 28 deletions(-) + +--- a/arch/arm/include/asm/futex.h ++++ b/arch/arm/include/asm/futex.h +@@ -3,11 +3,6 @@ + + #ifdef __KERNEL__ + +-#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP) +-/* ARM doesn't provide unprivileged exclusive memory accessors */ +-#include +-#else +- + #include + #include + #include +@@ -164,6 +159,5 @@ futex_atomic_op_inuser (int encoded_op, + return ret; + } + +-#endif /* !(CPU_USE_DOMAINS && SMP) */ + #endif /* __KERNEL__ */ + #endif /* _ASM_ARM_FUTEX_H */ +--- a/arch/arm/include/asm/pgtable-2level.h ++++ b/arch/arm/include/asm/pgtable-2level.h +@@ -140,6 +140,7 @@ + #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ + #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ + #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ ++#define L_PTE_MT_VECTORS (_AT(pteval_t, 0x0f) << 2) /* 1111 */ + #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) + + #ifndef __ASSEMBLY__ +--- a/arch/arm/mm/Kconfig ++++ b/arch/arm/mm/Kconfig +@@ -436,7 +436,6 @@ config CPU_32v5 + + config CPU_32v6 + bool +- select CPU_USE_DOMAINS if CPU_V6 && MMU + select TLS_REG_EMUL if !CPU_32v6K && !MMU + + config CPU_32v6K +@@ -651,7 +650,7 @@ config ARM_VIRT_EXT + + config SWP_EMULATE + bool "Emulate SWP/SWPB instructions" +- depends on !CPU_USE_DOMAINS && CPU_V7 ++ depends on CPU_V7 + default y if SMP + select HAVE_PROC_CPU if PROC_FS + help +--- a/arch/arm/mm/mmu.c ++++ b/arch/arm/mm/mmu.c +@@ -459,6 +459,16 @@ static void __init build_mem_type_table( + hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte; + + /* ++ * We don't use domains on ARMv6 (since this causes problems with ++ * v6/v7 kernels), so we must use a separate memory type for user ++ * r/o, kernel r/w to map the vectors page. ++ */ ++#ifndef CONFIG_ARM_LPAE ++ if (cpu_arch == CPU_ARCH_ARMv6) ++ vecs_pgprot |= L_PTE_MT_VECTORS; ++#endif ++ ++ /* + * ARMv6 and above have extended page tables. + */ + if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { +--- a/arch/arm/mm/proc-macros.S ++++ b/arch/arm/mm/proc-macros.S +@@ -112,13 +112,9 @@ + * 100x 1 0 1 r/o no acc + * 10x0 1 0 1 r/o no acc + * 1011 0 0 1 r/w no acc +- * 110x 0 1 0 r/w r/o +- * 11x0 0 1 0 r/w r/o +- * 1111 0 1 1 r/w r/w +- * +- * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed: + * 110x 1 1 1 r/o r/o + * 11x0 1 1 1 r/o r/o ++ * 1111 0 1 1 r/w r/w + */ + .macro armv6_mt_table pfx + \pfx\()_mt_table: +@@ -137,7 +133,7 @@ + .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED + .long 0x00 @ unused + .long 0x00 @ unused +- .long 0x00 @ unused ++ .long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS + .endm + + .macro armv6_set_pte_ext pfx +@@ -158,24 +154,21 @@ + + tst r1, #L_PTE_USER + orrne r3, r3, #PTE_EXT_AP1 +-#ifdef CONFIG_CPU_USE_DOMAINS +- @ allow kernel read/write access to read-only user pages + tstne r3, #PTE_EXT_APX +- bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 +-#endif ++ ++ @ user read-only -> kernel read-only ++ bicne r3, r3, #PTE_EXT_AP0 + + tst r1, #L_PTE_XN + orrne r3, r3, #PTE_EXT_XN + +- orr r3, r3, r2 ++ eor r3, r3, r2 + + tst r1, #L_PTE_YOUNG + tstne r1, #L_PTE_PRESENT + moveq r3, #0 +-#ifndef CONFIG_CPU_USE_DOMAINS + tstne r1, #L_PTE_NONE + movne r3, #0 +-#endif + + str r3, [r0] + mcr p15, 0, r0, c7, c10, 1 @ flush_pte +--- a/arch/arm/mm/proc-v7-2level.S ++++ b/arch/arm/mm/proc-v7-2level.S +@@ -90,21 +90,14 @@ ENTRY(cpu_v7_set_pte_ext) + + tst r1, #L_PTE_USER + orrne r3, r3, #PTE_EXT_AP1 +-#ifdef CONFIG_CPU_USE_DOMAINS +- @ allow kernel read/write access to read-only user pages +- tstne r3, #PTE_EXT_APX +- bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 +-#endif + + tst r1, #L_PTE_XN + orrne r3, r3, #PTE_EXT_XN + + tst r1, #L_PTE_YOUNG + tstne r1, #L_PTE_VALID +-#ifndef CONFIG_CPU_USE_DOMAINS + eorne r1, r1, #L_PTE_NONE + tstne r1, #L_PTE_NONE +-#endif + moveq r3, #0 + + ARM( str r3, [r0, #2048]! ) diff --git a/queue-3.10/arm-8007-1-remove-extraneous-kcmp-syscall-ignore.patch b/queue-3.10/arm-8007-1-remove-extraneous-kcmp-syscall-ignore.patch new file mode 100644 index 00000000000..b0e46ab841d --- /dev/null +++ b/queue-3.10/arm-8007-1-remove-extraneous-kcmp-syscall-ignore.patch @@ -0,0 +1,31 @@ +From 95c52fe063351192e0f4ffb70ef9bac1aa26f5a4 Mon Sep 17 00:00:00 2001 +From: Christopher Covington +Date: Wed, 19 Mar 2014 18:12:25 +0100 +Subject: ARM: 8007/1: Remove extraneous kcmp syscall ignore + +From: Christopher Covington + +commit 95c52fe063351192e0f4ffb70ef9bac1aa26f5a4 upstream. + +The kcmp system call was ported to ARM in +commit 3f7d1fe108dbaefd0c57a41753fc2c90b395f458 +"ARM: 7665/1: Wire up kcmp syscall". + +Fixes: 3f7d1fe108db ("ARM: 7665/1: Wire up kcmp syscall") +Signed-off-by: Christopher Covington +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/unistd.h | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm/include/asm/unistd.h ++++ b/arch/arm/include/asm/unistd.h +@@ -48,6 +48,5 @@ + */ + #define __IGNORE_fadvise64_64 + #define __IGNORE_migrate_pages +-#define __IGNORE_kcmp + + #endif /* __ASM_ARM_UNISTD_H */ diff --git a/queue-3.10/arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch b/queue-3.10/arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch new file mode 100644 index 00000000000..9756b2d5c76 --- /dev/null +++ b/queue-3.10/arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch @@ -0,0 +1,45 @@ +From 80bb3ef109ff40a7593d9481c17de9bbc4d7c0e2 Mon Sep 17 00:00:00 2001 +From: Xiangyu Lu +Date: Tue, 15 Apr 2014 09:38:17 +0100 +Subject: ARM: 8027/1: fix do_div() bug in big-endian systems + +From: Xiangyu Lu + +commit 80bb3ef109ff40a7593d9481c17de9bbc4d7c0e2 upstream. + +In big-endian systems, "%1" get the most significant part of the value, cause the instruction to get the wrong result. + +When viewing ftrace record in big-endian ARM systems, we found that +the timestamp errors: + +swapper-0 [001] 1325.970000: 0:120:R ==> [001] 16:120:R events/1 +events/1-16 [001] 1325.970000: 16:120:S ==> [001] 0:120:R swapper +swapper-0 [000] 1325.1000000: 0:120:R + [000] 15:120:R events/0 +swapper-0 [000] 1325.1000000: 0:120:R ==> [000] 15:120:R events/0 +swapper-0 [000] 1326.030000: 0:120:R + [000] 1150:120:R sshd +swapper-0 [000] 1326.030000: 0:120:R ==> [000] 1150:120:R sshd + +When viewed ftrace records, it will call the do_div(n, base) function, which achieved arch/arm/include/asm/div64.h in. When n = 10000000, base = 1000000, in do_div(n, base) will execute "umull %Q0, %R0, %1, %Q2". + +Reviewed-by: Dave Martin +Reviewed-by: Nicolas Pitre +Signed-off-by: Alex Wu +Signed-off-by: Xiangyu Lu +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/include/asm/div64.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/include/asm/div64.h ++++ b/arch/arm/include/asm/div64.h +@@ -156,7 +156,7 @@ + /* Select the best insn combination to perform the */ \ + /* actual __m * __n / (__p << 64) operation. */ \ + if (!__c) { \ +- asm ( "umull %Q0, %R0, %1, %Q2\n\t" \ ++ asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \ + "mov %Q0, #0" \ + : "=&r" (__res) \ + : "r" (__m), "r" (__n) \ diff --git a/queue-3.10/arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch b/queue-3.10/arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch new file mode 100644 index 00000000000..e44d790828b --- /dev/null +++ b/queue-3.10/arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch @@ -0,0 +1,38 @@ +From 56b700fd6f1e49149880fb1b6ffee0dca5be45fb Mon Sep 17 00:00:00 2001 +From: Liu Hua +Date: Fri, 18 Apr 2014 07:45:36 +0100 +Subject: ARM: 8030/1: ARM : kdump : add arch_crash_save_vmcoreinfo + +From: Liu Hua + +commit 56b700fd6f1e49149880fb1b6ffee0dca5be45fb upstream. + +For vmcore generated by LPAE enabled kernel, user space +utility such as crash needs additional infomation to +parse. + +So this patch add arch_crash_save_vmcoreinfo as what PAE enabled +i386 linux does. + +Reviewed-by: Will Deacon +Signed-off-by: Liu Hua +Signed-off-by: Russell King +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/kernel/machine_kexec.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/kernel/machine_kexec.c ++++ b/arch/arm/kernel/machine_kexec.c +@@ -169,3 +169,10 @@ void machine_kexec(struct kimage *image) + + soft_restart(reboot_code_buffer_phys); + } ++ ++void arch_crash_save_vmcoreinfo(void) ++{ ++#ifdef CONFIG_ARM_LPAE ++ VMCOREINFO_CONFIG(ARM_LPAE); ++#endif ++} diff --git a/queue-3.10/arm-dts-keep-g3d-regulator-always-on-for-exynos5250-arndale.patch b/queue-3.10/arm-dts-keep-g3d-regulator-always-on-for-exynos5250-arndale.patch new file mode 100644 index 00000000000..2c12c9024ec --- /dev/null +++ b/queue-3.10/arm-dts-keep-g3d-regulator-always-on-for-exynos5250-arndale.patch @@ -0,0 +1,44 @@ +From bfeda827278f09f4db35877e5f1ca9c149ca2890 Mon Sep 17 00:00:00 2001 +From: Tomasz Figa +Date: Fri, 14 Feb 2014 07:43:54 +0900 +Subject: ARM: dts: Keep G3D regulator always on for exynos5250-arndale + +From: Tomasz Figa + +commit bfeda827278f09f4db35877e5f1ca9c149ca2890 upstream. + +Apparently, if G3D regulator is powered off, the SoC cannot enter low +power modes and just hangs. This patch fixes this by keeping the +regulator always on when the system is running, as suggested by Exynos 4 +User's Manual in case of Exynos4210/4x12 SoCs (Exynos5250 UM does not +have such note, but observed behavior seems to confirm that it is true +for this SoC as well). + +This fixes an issue preventing Arndale board from entering sleep mode +observed since commit + +346f372f7b72a0 clk: exynos5250: Add CLK_IGNORE_UNUSED flag for pmu clock + +that landed in kernel 3.10, which has fixed the clock driver to make the +SoC actually try to enter the sleep mode. + +Signed-off-by: Tomasz Figa +Acked-by: Kyungmin Park +Tested-by: Tushar Behera +Signed-off-by: Kukjin Kim +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/exynos5250-arndale.dts | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/exynos5250-arndale.dts ++++ b/arch/arm/boot/dts/exynos5250-arndale.dts +@@ -263,6 +263,7 @@ + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; ++ regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; diff --git a/queue-3.10/arm-mvebu-ensure-the-mdio-node-has-a-clock-reference-on-armada-370-xp.patch b/queue-3.10/arm-mvebu-ensure-the-mdio-node-has-a-clock-reference-on-armada-370-xp.patch new file mode 100644 index 00000000000..14b7ca28cf3 --- /dev/null +++ b/queue-3.10/arm-mvebu-ensure-the-mdio-node-has-a-clock-reference-on-armada-370-xp.patch @@ -0,0 +1,37 @@ +From a6e03dd451c724f785277d8ecca5d1a0b886d892 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Wed, 26 Mar 2014 00:33:58 +0100 +Subject: ARM: mvebu: ensure the mdio node has a clock reference on Armada 370/XP + +From: Thomas Petazzoni + +commit a6e03dd451c724f785277d8ecca5d1a0b886d892 upstream. + +The mvmdio driver accesses some register of the Ethernet unit. It +therefore takes a reference and enables a clock. However, on Armada +370/XP, no clock specification was given in the Device Tree, which +leads the mvmdio driver to fail when being used as a module and loaded +before the mvneta driver: it tries to access a register from a +hardware unit that isn't clocked. + +Signed-off-by: Thomas Petazzoni +Link: https://lkml.kernel.org/r/1395790439-21332-2-git-send-email-thomas.petazzoni@free-electrons.com +Acked-by: Andrew Lunn +Acked-by: Gregory CLEMENT +Signed-off-by: Jason Cooper +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/boot/dts/armada-370-xp.dtsi | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/boot/dts/armada-370-xp.dtsi ++++ b/arch/arm/boot/dts/armada-370-xp.dtsi +@@ -92,6 +92,7 @@ + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x72004 0x4>; ++ clocks = <&gateclk 4>; + }; + + ethernet@70000 { diff --git a/queue-3.10/arm-omap2-intc-acknowledge-stuck-active-interrupts.patch b/queue-3.10/arm-omap2-intc-acknowledge-stuck-active-interrupts.patch new file mode 100644 index 00000000000..d64eea55d36 --- /dev/null +++ b/queue-3.10/arm-omap2-intc-acknowledge-stuck-active-interrupts.patch @@ -0,0 +1,57 @@ +From 698b48532539484b012fb7c4176b959d32a17d00 Mon Sep 17 00:00:00 2001 +From: Stefan Sørensen +Date: Thu, 6 Mar 2014 16:27:15 +0100 +Subject: ARM: OMAP2+: INTC: Acknowledge stuck active interrupts +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Stefan Sørensen + +commit 698b48532539484b012fb7c4176b959d32a17d00 upstream. + +When an interrupt has become active on the INTC it will stay active +until it is acked, even if masked or de-asserted. The +INTC_PENDING_IRQn registers are however updated and since these are +used by omap_intc_handle_irq to determine which interrupt to handle, +it will never see the active interrupt. This will result in a storm of +useless interrupts that is only stopped when another higher priority +interrupt is asserted. + +Fix by sending the INTC an acknowledge if we find no interrupts to +handle. + +Signed-off-by: Stefan Sørensen +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-omap2/irq.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/arch/arm/mach-omap2/irq.c ++++ b/arch/arm/mach-omap2/irq.c +@@ -222,6 +222,7 @@ void __init ti81xx_init_irq(void) + static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs) + { + u32 irqnr; ++ int handled_irq = 0; + + do { + irqnr = readl_relaxed(base_addr + 0x98); +@@ -249,8 +250,15 @@ out: + if (irqnr) { + irqnr = irq_find_mapping(domain, irqnr); + handle_IRQ(irqnr, regs); ++ handled_irq = 1; + } + } while (irqnr); ++ ++ /* If an irq is masked or deasserted while active, we will ++ * keep ending up here with no irq handled. So remove it from ++ * the INTC with an ack.*/ ++ if (!handled_irq) ++ omap_ack_irq(NULL); + } + + asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs) diff --git a/queue-3.10/arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch b/queue-3.10/arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch new file mode 100644 index 00000000000..f04b1026f51 --- /dev/null +++ b/queue-3.10/arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch @@ -0,0 +1,49 @@ +From c6c56697ae4bf1226263c19e8353343d7083f40e Mon Sep 17 00:00:00 2001 +From: Roger Quadros +Date: Thu, 10 Apr 2014 10:18:17 +0300 +Subject: ARM: OMAP3: hwmod data: Correct clock domains for USB modules + +From: Roger Quadros + +commit c6c56697ae4bf1226263c19e8353343d7083f40e upstream. + +OMAP3 doesn't contain "l3_init_clkdm" clock domain. Use the +proper clock domains for USB Host and USB TLL modules. + +Gets rid of the following warnings during boot + omap_hwmod: usb_host_hs: could not associate to clkdm l3_init_clkdm + omap_hwmod: usb_tll_hs: could not associate to clkdm l3_init_clkdm + +Reported-by: Nishanth Menon +Cc: Paul Walmsley +Signed-off-by: Roger Quadros +Fixes: de231388cb80a8ef3e779bbfa0564ba0157b7377 ("ARM: OMAP: USB: EHCI and OHCI hwmod structures for OMAP3") +Cc: Keshava Munegowda +Cc: Partha Basak +Signed-off-by: Paul Walmsley +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c ++++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +@@ -1955,7 +1955,7 @@ static struct omap_hwmod_irq_info omap3x + static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = { + .name = "usb_host_hs", + .class = &omap3xxx_usb_host_hs_hwmod_class, +- .clkdm_name = "l3_init_clkdm", ++ .clkdm_name = "usbhost_clkdm", + .mpu_irqs = omap3xxx_usb_host_hs_irqs, + .main_clk = "usbhost_48m_fck", + .prcm = { +@@ -2040,7 +2040,7 @@ static struct omap_hwmod_irq_info omap3x + static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = { + .name = "usb_tll_hs", + .class = &omap3xxx_usb_tll_hs_hwmod_class, +- .clkdm_name = "l3_init_clkdm", ++ .clkdm_name = "core_l4_clkdm", + .mpu_irqs = omap3xxx_usb_tll_hs_irqs, + .main_clk = "usbtll_fck", + .prcm = { diff --git a/queue-3.10/arm-omap4-fix-definition-of-is_pm44xx_erratum.patch b/queue-3.10/arm-omap4-fix-definition-of-is_pm44xx_erratum.patch new file mode 100644 index 00000000000..977dce68a92 --- /dev/null +++ b/queue-3.10/arm-omap4-fix-definition-of-is_pm44xx_erratum.patch @@ -0,0 +1,38 @@ +From 07484ca33ef83900f5cfbde075c1a19e5a237aa1 Mon Sep 17 00:00:00 2001 +From: Nishanth Menon +Date: Wed, 12 Mar 2014 16:43:20 -0500 +Subject: ARM: OMAP4: Fix definition of IS_PM44XX_ERRATUM + +From: Nishanth Menon + +commit 07484ca33ef83900f5cfbde075c1a19e5a237aa1 upstream. + +Just like IS_PM34XX_ERRATUM, IS_PM44XX_ERRATUM is valid only if +CONFIG_PM is enabled, else, disabling CONFIG_PM results in build +failure complaining about the following: +arch/arm/mach-omap2/built-in.o: In function `omap4_boot_secondary': +:(.text+0x8a70): undefined reference to `pm44xx_errata' + +Fixes: c962184 (ARM: OMAP4: PM: add errata support) +Reported-by: Tony Lindgren +Signed-off-by: Nishanth Menon +Acked-by: Santosh Shilimkar +Acked-by: Kevin Hilman +Signed-off-by: Tony Lindgren +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-omap2/pm.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm/mach-omap2/pm.h ++++ b/arch/arm/mach-omap2/pm.h +@@ -103,7 +103,7 @@ static inline void enable_omap3630_toggl + + #define PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD (1 << 0) + +-#if defined(CONFIG_ARCH_OMAP4) ++#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) + extern u16 pm44xx_errata; + #define IS_PM44XX_ERRATUM(id) (pm44xx_errata & (id)) + #else diff --git a/queue-3.10/arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch b/queue-3.10/arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch new file mode 100644 index 00000000000..98a71aa205f --- /dev/null +++ b/queue-3.10/arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch @@ -0,0 +1,37 @@ +From c02b50e90be9f41d6802049a1a08246e9eb1a22c Mon Sep 17 00:00:00 2001 +From: Andrea Adami +Date: Tue, 8 Apr 2014 14:53:44 +0200 +Subject: ARM: pxa: hx4700.h: include "irqs.h" for PXA_NR_BUILTIN_GPIO + +From: Andrea Adami + +commit c02b50e90be9f41d6802049a1a08246e9eb1a22c upstream. + +hx4700 needs the same fix as in +9705e74671f0e4f994d86b00cecf441917c64a66 +"ARM: pxa: fix various compilation problems" + +Fix build errors. Initial one is: +/linux/arch/arm/mach-pxa/include/mach/hx4700.h:18:32: error: + 'PXA_NR_BUILTIN_GPIO' undeclared here (not in a function) +| #define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO + +Signed-off-by: Andrea Adami +Signed-off-by: Linus Walleij +Signed-off-by: Arnd Bergmann +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm/mach-pxa/include/mach/hx4700.h | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/arm/mach-pxa/include/mach/hx4700.h ++++ b/arch/arm/mach-pxa/include/mach/hx4700.h +@@ -14,6 +14,7 @@ + + #include + #include ++#include "irqs.h" /* PXA_NR_BUILTIN_GPIO */ + + #define HX4700_ASIC3_GPIO_BASE PXA_NR_BUILTIN_GPIO + #define HX4700_EGPIO_BASE (HX4700_ASIC3_GPIO_BASE + ASIC3_NUM_GPIOS) diff --git a/queue-3.10/arm64-do-not-synchronise-i-and-d-caches-for-special-ptes.patch b/queue-3.10/arm64-do-not-synchronise-i-and-d-caches-for-special-ptes.patch new file mode 100644 index 00000000000..a8c8557b7e6 --- /dev/null +++ b/queue-3.10/arm64-do-not-synchronise-i-and-d-caches-for-special-ptes.patch @@ -0,0 +1,34 @@ +From 71fdb6bf61bf0692f004f9daf5650392c0cfe300 Mon Sep 17 00:00:00 2001 +From: Catalin Marinas +Date: Wed, 12 Mar 2014 16:28:09 +0000 +Subject: arm64: Do not synchronise I and D caches for special ptes + +From: Catalin Marinas + +commit 71fdb6bf61bf0692f004f9daf5650392c0cfe300 upstream. + +Special pte mappings are not intended to be executable and do not even +have an associated struct page. This patch ensures that we do not call +__sync_icache_dcache() on such ptes. + +Signed-off-by: Catalin Marinas +Reported-by: Steve Capper +Tested-by: Laura Abbott +Tested-by: Bharat Bhushan +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/asm/pgtable.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/include/asm/pgtable.h ++++ b/arch/arm64/include/asm/pgtable.h +@@ -161,7 +161,7 @@ static inline void set_pte_at(struct mm_ + pte_t *ptep, pte_t pte) + { + if (pte_valid_user(pte)) { +- if (pte_exec(pte)) ++ if (!pte_special(pte) && pte_exec(pte)) + __sync_icache_dcache(pte, addr); + if (!pte_dirty(pte)) + pte = pte_wrprotect(pte); diff --git a/queue-3.10/arm64-make-dma-coherent-and-strongly-ordered-mappings-not-executable.patch b/queue-3.10/arm64-make-dma-coherent-and-strongly-ordered-mappings-not-executable.patch new file mode 100644 index 00000000000..af4c2f222f2 --- /dev/null +++ b/queue-3.10/arm64-make-dma-coherent-and-strongly-ordered-mappings-not-executable.patch @@ -0,0 +1,40 @@ +From de2db7432917a82b62d55bb59635586eeca6d1bd Mon Sep 17 00:00:00 2001 +From: Catalin Marinas +Date: Wed, 12 Mar 2014 16:07:06 +0000 +Subject: arm64: Make DMA coherent and strongly ordered mappings not executable + +From: Catalin Marinas + +commit de2db7432917a82b62d55bb59635586eeca6d1bd upstream. + +pgprot_{dmacoherent,writecombine,noncached} don't need to generate +executable mappings with side-effects like __sync_icache_dcache() being +called when the mapping is in user space. + +Signed-off-by: Catalin Marinas +Reported-by: Bharat Bhushan +Tested-by: Laura Abbott +Tested-by: Bharat Bhushan +Signed-off-by: Greg Kroah-Hartman + +--- + arch/arm64/include/asm/pgtable.h | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/arch/arm64/include/asm/pgtable.h ++++ b/arch/arm64/include/asm/pgtable.h +@@ -182,11 +182,11 @@ static inline void set_pte_at(struct mm_ + * Mark the prot value as uncacheable and unbufferable. + */ + #define pgprot_noncached(prot) \ +- __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE)) ++ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) + #define pgprot_writecombine(prot) \ +- __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) ++ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) + #define pgprot_dmacoherent(prot) \ +- __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) ++ __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) + #define __HAVE_PHYS_MEM_ACCESS_PROT + struct file; + extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, diff --git a/queue-3.10/asoc-cs42l51-fix-soc_double_r_sx_tlv-shift-values-for-adc-pcm-and-analog-kcontrols.patch b/queue-3.10/asoc-cs42l51-fix-soc_double_r_sx_tlv-shift-values-for-adc-pcm-and-analog-kcontrols.patch new file mode 100644 index 00000000000..d61b8a2181f --- /dev/null +++ b/queue-3.10/asoc-cs42l51-fix-soc_double_r_sx_tlv-shift-values-for-adc-pcm-and-analog-kcontrols.patch @@ -0,0 +1,54 @@ +From 7272e051157ccd5871b5d939548d0ba5a94a2965 Mon Sep 17 00:00:00 2001 +From: Brian Austin +Date: Wed, 19 Mar 2014 10:40:02 -0500 +Subject: ASoC: cs42l51: Fix SOC_DOUBLE_R_SX_TLV shift values for ADC, PCM, and Analog kcontrols + +From: Brian Austin + +commit 7272e051157ccd5871b5d939548d0ba5a94a2965 upstream. + +The shift values for the ADC,PCM, and Analog kcontrols were wrong causing wrong values for the SOC_DOUBLE_R_SX_TLV macros +Fixed the TLV for aout_tlv to show -102dB correctly + +Fixes: 1d99f2436d (ASoC: core: Rework SOC_DOUBLE_R_SX_TLV add SOC_SINGLE_SX_TLV) +Reported-by: Thomas Petazzoni +Signed-off-by: Brian Austin +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/cs42l51.c | 9 ++++----- + 1 file changed, 4 insertions(+), 5 deletions(-) + +--- a/sound/soc/codecs/cs42l51.c ++++ b/sound/soc/codecs/cs42l51.c +@@ -124,9 +124,8 @@ static int cs42l51_set_chan_mix(struct s + + static const DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -5150, 50, 0); + static const DECLARE_TLV_DB_SCALE(tone_tlv, -1050, 150, 0); +-/* This is a lie. after -102 db, it stays at -102 */ +-/* maybe a range would be better */ +-static const DECLARE_TLV_DB_SCALE(aout_tlv, -11550, 50, 0); ++ ++static const DECLARE_TLV_DB_SCALE(aout_tlv, -10200, 50, 0); + + static const DECLARE_TLV_DB_SCALE(boost_tlv, 1600, 1600, 0); + static const char *chan_mix[] = { +@@ -141,7 +140,7 @@ static const struct soc_enum cs42l51_cha + static const struct snd_kcontrol_new cs42l51_snd_controls[] = { + SOC_DOUBLE_R_SX_TLV("PCM Playback Volume", + CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, +- 6, 0x19, 0x7F, adc_pcm_tlv), ++ 0, 0x19, 0x7F, adc_pcm_tlv), + SOC_DOUBLE_R("PCM Playback Switch", + CS42L51_PCMA_VOL, CS42L51_PCMB_VOL, 7, 1, 1), + SOC_DOUBLE_R_SX_TLV("Analog Playback Volume", +@@ -149,7 +148,7 @@ static const struct snd_kcontrol_new cs4 + 0, 0x34, 0xE4, aout_tlv), + SOC_DOUBLE_R_SX_TLV("ADC Mixer Volume", + CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, +- 6, 0x19, 0x7F, adc_pcm_tlv), ++ 0, 0x19, 0x7F, adc_pcm_tlv), + SOC_DOUBLE_R("ADC Mixer Switch", + CS42L51_ADCA_VOL, CS42L51_ADCB_VOL, 7, 1, 1), + SOC_SINGLE("Playback Deemphasis Switch", CS42L51_DAC_CTL, 3, 1, 0), diff --git a/queue-3.10/asoc-cs42l52-fix-mask-bits-for-soc_value_enum_single.patch b/queue-3.10/asoc-cs42l52-fix-mask-bits-for-soc_value_enum_single.patch new file mode 100644 index 00000000000..ada02c28403 --- /dev/null +++ b/queue-3.10/asoc-cs42l52-fix-mask-bits-for-soc_value_enum_single.patch @@ -0,0 +1,58 @@ +From d31a33dd7792c7d6c11fda226a3b9e4fb7f86f95 Mon Sep 17 00:00:00 2001 +From: Brian Austin +Date: Tue, 18 Mar 2014 14:01:47 -0500 +Subject: ASoC: cs42l52: Fix mask bits for SOC_VALUE_ENUM_SINGLE + +From: Brian Austin + +commit d31a33dd7792c7d6c11fda226a3b9e4fb7f86f95 upstream. + +The mask bits values were wrong for the SOC_VALUE_ENUM_SINGLE for the PCM/ADC Swap controls + +Reported-by: Takashi Iwai +Signed-off-by: Brian Austin +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/cs42l52.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/sound/soc/codecs/cs42l52.c ++++ b/sound/soc/codecs/cs42l52.c +@@ -350,7 +350,7 @@ static const char * const right_swap_tex + static const unsigned int swap_values[] = { 0, 1, 3 }; + + static const struct soc_enum adca_swap_enum = +- SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 1, ++ SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 2, 3, + ARRAY_SIZE(left_swap_text), + left_swap_text, + swap_values); +@@ -359,7 +359,7 @@ static const struct snd_kcontrol_new adc + SOC_DAPM_ENUM("Route", adca_swap_enum); + + static const struct soc_enum pcma_swap_enum = +- SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 1, ++ SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 6, 3, + ARRAY_SIZE(left_swap_text), + left_swap_text, + swap_values); +@@ -368,7 +368,7 @@ static const struct snd_kcontrol_new pcm + SOC_DAPM_ENUM("Route", pcma_swap_enum); + + static const struct soc_enum adcb_swap_enum = +- SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 1, ++ SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 0, 3, + ARRAY_SIZE(right_swap_text), + right_swap_text, + swap_values); +@@ -377,7 +377,7 @@ static const struct snd_kcontrol_new adc + SOC_DAPM_ENUM("Route", adcb_swap_enum); + + static const struct soc_enum pcmb_swap_enum = +- SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 1, ++ SOC_VALUE_ENUM_SINGLE(CS42L52_ADC_PCM_MIXER, 4, 3, + ARRAY_SIZE(right_swap_text), + right_swap_text, + swap_values); diff --git a/queue-3.10/asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch b/queue-3.10/asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch new file mode 100644 index 00000000000..9375bc45f77 --- /dev/null +++ b/queue-3.10/asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch @@ -0,0 +1,49 @@ +From 1555b652970e541fa1cb80c61ffc696bbfb92bb7 Mon Sep 17 00:00:00 2001 +From: Brian Austin +Date: Tue, 18 Mar 2014 13:56:21 -0500 +Subject: ASoC: cs42l73: Fix mask bits for SOC_VALUE_ENUM_SINGLE + +From: Brian Austin + +commit 1555b652970e541fa1cb80c61ffc696bbfb92bb7 upstream. + +The mask bits values were wrong for the SOC_VALUE_ENUM_SINGLE for the mono mix controls. + +Reported-by: Takashi Iwai +Signed-off-by: Brian Austin +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman + +--- + sound/soc/codecs/cs42l73.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/sound/soc/codecs/cs42l73.c ++++ b/sound/soc/codecs/cs42l73.c +@@ -325,7 +325,7 @@ static const char * const cs42l73_mono_m + static const unsigned int cs42l73_mono_mix_values[] = { 0, 1, 2 }; + + static const struct soc_enum spk_asp_enum = +- SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 1, ++ SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 6, 3, + ARRAY_SIZE(cs42l73_mono_mix_texts), + cs42l73_mono_mix_texts, + cs42l73_mono_mix_values); +@@ -343,7 +343,7 @@ static const struct snd_kcontrol_new spk + SOC_DAPM_ENUM("Route", spk_xsp_enum); + + static const struct soc_enum esl_asp_enum = +- SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 5, ++ SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 2, 3, + ARRAY_SIZE(cs42l73_mono_mix_texts), + cs42l73_mono_mix_texts, + cs42l73_mono_mix_values); +@@ -352,7 +352,7 @@ static const struct snd_kcontrol_new esl + SOC_DAPM_ENUM("Route", esl_asp_enum); + + static const struct soc_enum esl_xsp_enum = +- SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 7, ++ SOC_VALUE_ENUM_SINGLE(CS42L73_MMIXCTL, 0, 3, + ARRAY_SIZE(cs42l73_mono_mix_texts), + cs42l73_mono_mix_texts, + cs42l73_mono_mix_values); diff --git a/queue-3.10/series b/queue-3.10/series new file mode 100644 index 00000000000..a320f7b50fa --- /dev/null +++ b/queue-3.10/series @@ -0,0 +1,16 @@ +arm64-do-not-synchronise-i-and-d-caches-for-special-ptes.patch +arm64-make-dma-coherent-and-strongly-ordered-mappings-not-executable.patch +asoc-cs42l51-fix-soc_double_r_sx_tlv-shift-values-for-adc-pcm-and-analog-kcontrols.patch +asoc-cs42l52-fix-mask-bits-for-soc_value_enum_single.patch +asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch +arm-omap2-intc-acknowledge-stuck-active-interrupts.patch +arm-omap4-fix-definition-of-is_pm44xx_erratum.patch +arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch +arm-dts-keep-g3d-regulator-always-on-for-exynos5250-arndale.patch +arm-7954-1-mm-remove-remaining-domain-support-from-armv6.patch +arm-8007-1-remove-extraneous-kcmp-syscall-ignore.patch +arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch +arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch +arm-mvebu-ensure-the-mdio-node-has-a-clock-reference-on-armada-370-xp.patch +arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch +arm-7728-1-mm-use-phys_addr_t-properly-for-ioremap-functions.patch diff --git a/queue-3.14/series b/queue-3.14/series new file mode 100644 index 00000000000..29283285ef2 --- /dev/null +++ b/queue-3.14/series @@ -0,0 +1,21 @@ +arm64-do-not-synchronise-i-and-d-caches-for-special-ptes.patch +arm64-make-dma-coherent-and-strongly-ordered-mappings-not-executable.patch +asoc-pcm-drop-incorrect-double-extra-frees.patch +asoc-cs42l51-fix-soc_double_r_sx_tlv-shift-values-for-adc-pcm-and-analog-kcontrols.patch +asoc-cs42l52-fix-mask-bits-for-soc_value_enum_single.patch +asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch +arm-omap2-intc-acknowledge-stuck-active-interrupts.patch +arm-omap2-hwmod-fix-missing-braces-in-_init.patch +clk-ti-omap4-5-dra7-remove-gpmc_fck-from-dummy-clocks.patch +arm-omap4-fix-definition-of-is_pm44xx_erratum.patch +arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch +arm-dts-am33xx-correcting-dt-node-unit-address-for-usb.patch +arm-dts-omap4-5-use-l3_ick-for-the-gpmc-node.patch +arm-dts-keep-g3d-regulator-always-on-for-exynos5250-arndale.patch +arm-7954-1-mm-remove-remaining-domain-support-from-armv6.patch +arm-fix-default-cpu-selection-for-arch_multi_v5.patch +arm-8007-1-remove-extraneous-kcmp-syscall-ignore.patch +arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch +arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch +arm-mvebu-ensure-the-mdio-node-has-a-clock-reference-on-armada-370-xp.patch +arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch diff --git a/queue-3.4/series b/queue-3.4/series new file mode 100644 index 00000000000..3b2871f0c20 --- /dev/null +++ b/queue-3.4/series @@ -0,0 +1,6 @@ +asoc-cs42l73-fix-mask-bits-for-soc_value_enum_single.patch +arm-omap2-intc-acknowledge-stuck-active-interrupts.patch +arm-omap3-hwmod-data-correct-clock-domains-for-usb-modules.patch +arm-8027-1-fix-do_div-bug-in-big-endian-systems.patch +arm-8030-1-arm-kdump-add-arch_crash_save_vmcoreinfo.patch +arm-pxa-hx4700.h-include-irqs.h-for-pxa_nr_builtin_gpio.patch -- 2.47.3