From 876d35eda3c330c7cc654657168c54bc6d0d6e4e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sat, 15 Apr 2023 20:42:24 +0200 Subject: [PATCH] 5.15-stable patches added patches: drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch kvm-arm64-pmu-restore-the-guest-s-el0-event-counting-after-migration.patch --- ...fix-dss-ctl-register-offsets-for-tgl.patch | 76 +++++++++++++++++++ ...s-el0-event-counting-after-migration.patch | 57 ++++++++++++++ queue-5.15/series | 2 + 3 files changed, 135 insertions(+) create mode 100644 queue-5.15/drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch create mode 100644 queue-5.15/kvm-arm64-pmu-restore-the-guest-s-el0-event-counting-after-migration.patch diff --git a/queue-5.15/drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch b/queue-5.15/drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch new file mode 100644 index 00000000000..f1be95a8dbc --- /dev/null +++ b/queue-5.15/drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch @@ -0,0 +1,76 @@ +From 6b8446859c971a5783a2cdc90adf32e64de3bd23 Mon Sep 17 00:00:00 2001 +From: Jani Nikula +Date: Wed, 1 Mar 2023 17:14:09 +0200 +Subject: drm/i915/dsi: fix DSS CTL register offsets for TGL+ +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Jani Nikula + +commit 6b8446859c971a5783a2cdc90adf32e64de3bd23 upstream. + +On TGL+ the DSS control registers are at different offsets, and there's +one per pipe. Fix the offsets to fix dual link DSI for TGL+. + +There would be helpers for this in the DSC code, but just do the quick +fix now for DSI. Long term, we should probably move all the DSS handling +into intel_vdsc.c, so exporting the helpers seems counter-productive. + +Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8232 +Cc: Ville Syrjala +Cc: stable@vger.kernel.org +Signed-off-by: Jani Nikula +Reviewed-by: Ville Syrjälä +Link: https://patchwork.freedesktop.org/patch/msgid/20230301151409.1581574-1-jani.nikula@intel.com +(cherry picked from commit 1a62dd9895dca78bee28bba3a36f08836fdd143d) +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/i915/display/icl_dsi.c | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/i915/display/icl_dsi.c ++++ b/drivers/gpu/drm/i915/display/icl_dsi.c +@@ -307,9 +307,21 @@ static void configure_dual_link_mode(str + { + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); ++ i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1; + +- dss_ctl1 = intel_de_read(dev_priv, DSS_CTL1); ++ /* FIXME: Move all DSS handling to intel_vdsc.c */ ++ if (DISPLAY_VER(dev_priv) >= 12) { ++ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); ++ ++ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); ++ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); ++ } else { ++ dss_ctl1_reg = DSS_CTL1; ++ dss_ctl2_reg = DSS_CTL2; ++ } ++ ++ dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); + dss_ctl1 |= SPLITTER_ENABLE; + dss_ctl1 &= ~OVERLAP_PIXELS_MASK; + dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); +@@ -330,16 +342,16 @@ static void configure_dual_link_mode(str + + dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK; + dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); +- dss_ctl2 = intel_de_read(dev_priv, DSS_CTL2); ++ dss_ctl2 = intel_de_read(dev_priv, dss_ctl2_reg); + dss_ctl2 &= ~RIGHT_DL_BUF_TARGET_DEPTH_MASK; + dss_ctl2 |= RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth); +- intel_de_write(dev_priv, DSS_CTL2, dss_ctl2); ++ intel_de_write(dev_priv, dss_ctl2_reg, dss_ctl2); + } else { + /* Interleave */ + dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE; + } + +- intel_de_write(dev_priv, DSS_CTL1, dss_ctl1); ++ intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1); + } + + /* aka DSI 8X clock */ diff --git a/queue-5.15/kvm-arm64-pmu-restore-the-guest-s-el0-event-counting-after-migration.patch b/queue-5.15/kvm-arm64-pmu-restore-the-guest-s-el0-event-counting-after-migration.patch new file mode 100644 index 00000000000..13ce1291e7b --- /dev/null +++ b/queue-5.15/kvm-arm64-pmu-restore-the-guest-s-el0-event-counting-after-migration.patch @@ -0,0 +1,57 @@ +From f9ea835e99bc8d049bf2a3ec8fa5a7cb4fcade23 Mon Sep 17 00:00:00 2001 +From: Reiji Watanabe +Date: Tue, 28 Mar 2023 19:39:44 -0700 +Subject: KVM: arm64: PMU: Restore the guest's EL0 event counting after migration + +From: Reiji Watanabe + +commit f9ea835e99bc8d049bf2a3ec8fa5a7cb4fcade23 upstream. + +Currently, with VHE, KVM enables the EL0 event counting for the +guest on vcpu_load() or KVM enables it as a part of the PMU +register emulation process, when needed. However, in the migration +case (with VHE), the same handling is lacking, as vPMU register +values that were restored by userspace haven't been propagated yet +(the PMU events haven't been created) at the vcpu load-time on the +first KVM_RUN (kvm_vcpu_pmu_restore_guest() called from vcpu_load() +on the first KVM_RUN won't do anything as events_{guest,host} of +kvm_pmu_events are still zero). + +So, with VHE, enable the guest's EL0 event counting on the first +KVM_RUN (after the migration) when needed. More specifically, +have kvm_pmu_handle_pmcr() call kvm_vcpu_pmu_restore_guest() +so that kvm_pmu_handle_pmcr() on the first KVM_RUN can take +care of it. + +Fixes: d0c94c49792c ("KVM: arm64: Restore PMU configuration on first run") +Cc: stable@vger.kernel.org +Reviewed-by: Marc Zyngier +Signed-off-by: Reiji Watanabe +Link: https://lore.kernel.org/r/20230329023944.2488484-1-reijiw@google.com +Signed-off-by: Oliver Upton +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/kvm/pmu-emul.c | 1 + + arch/arm64/kvm/sys_regs.c | 1 - + 2 files changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/arm64/kvm/pmu-emul.c ++++ b/arch/arm64/kvm/pmu-emul.c +@@ -554,6 +554,7 @@ void kvm_pmu_software_increment(struct k + __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i); + } + } ++ kvm_vcpu_pmu_restore_guest(vcpu); + } + + /** +--- a/arch/arm64/kvm/sys_regs.c ++++ b/arch/arm64/kvm/sys_regs.c +@@ -702,7 +702,6 @@ static bool access_pmcr(struct kvm_vcpu + val |= ARMV8_PMU_PMCR_LC; + __vcpu_sys_reg(vcpu, PMCR_EL0) = val; + kvm_pmu_handle_pmcr(vcpu, val); +- kvm_vcpu_pmu_restore_guest(vcpu); + } else { + /* PMCR.P & PMCR.C are RAZ */ + val = __vcpu_sys_reg(vcpu, PMCR_EL0) diff --git a/queue-5.15/series b/queue-5.15/series index dc4550c7a7f..90965e1da04 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -14,3 +14,5 @@ mtdblock-tolerate-corrected-bit-flips.patch mtd-rawnand-meson-fix-bitmask-for-length-in-command-word.patch mtd-rawnand-stm32_fmc2-remove-unsupported-edo-mode.patch mtd-rawnand-stm32_fmc2-use-timings.mode-instead-of-checking-trc_min.patch +kvm-arm64-pmu-restore-the-guest-s-el0-event-counting-after-migration.patch +drm-i915-dsi-fix-dss-ctl-register-offsets-for-tgl.patch -- 2.47.3