From 880aa4cb06ff5e86b6feab3030e14a16fea1dced Mon Sep 17 00:00:00 2001 From: Glenn Miles Date: Thu, 25 Sep 2025 15:17:43 -0500 Subject: [PATCH] target/ppc: Support for IBM PPE42 MMU The IBM PPE42 processor only supports real mode addressing and does not distinguish between problem and supervisor states. It also uses the IR and DR MSR bits for other purposes. Therefore, add a check for PPE42 when we update hflags and cause it to ignore the IR and DR bits when calculating MMU indexes. Signed-off-by: Glenn Miles Reviewed-by: Chinmay Rath Signed-off-by: Harsh Prateek Bora Link: https://lore.kernel.org/r/20250925201758.652077-6-milesg@linux.ibm.com Message-ID: <20250925201758.652077-6-milesg@linux.ibm.com> --- target/ppc/helper_regs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index 41b7b939ec7..a07e6a7b7b6 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -186,6 +186,10 @@ static uint32_t hreg_compute_hflags_value(CPUPPCState *env) if (env->spr[SPR_LPCR] & LPCR_HR) { hflags |= 1 << HFLAGS_HR; } + if (unlikely(ppc_flags & POWERPC_FLAG_PPE42)) { + /* PPE42 has a single address space and no problem state */ + msr = 0; + } #ifndef CONFIG_USER_ONLY if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { -- 2.47.3