From 88d8515fb76ca7b3de8a4cc89264e8494655567e Mon Sep 17 00:00:00 2001 From: Jamin Lin Date: Thu, 15 May 2025 16:09:58 +0800 Subject: [PATCH] test/qtest/hace: Support to test upper 32 bits of digest and source addresses MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Added "src_hi" and "dest_hi" fields to "AspeedMasks" for 64-bit addresses test. Updated "aspeed_test_addresses" to validate "HACE_HASH_SRC_HI" and "HACE_HASH_DIGEST_HI". Ensured correct masking of 64-bit addresses by checking both lower and upper 32-bit registers. Signed-off-by: Jamin Lin Reviewed-by: Cédric Le Goater Acked-by: Fabiano Rosas Link: https://lore.kernel.org/qemu-devel/20250515081008.583578-27-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater --- tests/qtest/aspeed-hace-utils.c | 15 ++++++++++++++- tests/qtest/aspeed-hace-utils.h | 2 ++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tests/qtest/aspeed-hace-utils.c b/tests/qtest/aspeed-hace-utils.c index 842bf5630d..cb78f18117 100644 --- a/tests/qtest/aspeed-hace-utils.c +++ b/tests/qtest/aspeed-hace-utils.c @@ -588,30 +588,43 @@ void aspeed_test_addresses(const char *machine, const uint32_t base, */ g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); - /* Check that the address masking is correct */ qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src); + qtest_writel(s, base + HACE_HASH_SRC_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), + ==, expected->src_hi); + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, expected->dest); + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, + expected->dest_hi); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, expected->len); /* Reset to zero */ qtest_writel(s, base + HACE_HASH_SRC, 0); + qtest_writel(s, base + HACE_HASH_SRC_HI, 0); qtest_writel(s, base + HACE_HASH_DIGEST, 0); + qtest_writel(s, base + HACE_HASH_DIGEST_HI, 0); qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); /* Check that all bits are now zero */ g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST_HI), ==, 0); g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); qtest_quit(s); diff --git a/tests/qtest/aspeed-hace-utils.h b/tests/qtest/aspeed-hace-utils.h index d8684d3f83..de8055a1db 100644 --- a/tests/qtest/aspeed-hace-utils.h +++ b/tests/qtest/aspeed-hace-utils.h @@ -51,6 +51,8 @@ struct AspeedMasks { uint32_t src; uint32_t dest; uint32_t len; + uint32_t src_hi; + uint32_t dest_hi; }; void aspeed_test_md5(const char *machine, const uint32_t base, -- 2.39.5