From 8d8d73b55144e0d8d3c15a83a8fd8f3de78c460d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 26 Feb 2022 01:29:42 -1000 Subject: [PATCH] target/nios2: Special case ipending in rdctl and wrctl MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit It was never correct to be able to write to ipending. Until the rest of the irq code is tidied, the read of ipending will generate an "unnecessary" mask. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/nios2/translate.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 52965ba17ea..a5f8d207293 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -452,6 +452,17 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) } switch (instr.imm5 + CR_BASE) { + case CR_IPENDING: + /* + * The value of the ipending register is synthetic. + * In hw, this is the AND of a set of hardware irq lines + * with the ienable register. In qemu, we re-use the space + * of CR_IPENDING to store the set of irq lines, and so we + * must perform the AND here, and anywhere else we need the + * guest value of ipending. + */ + tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]); + break; default: tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); break; @@ -477,6 +488,9 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) case CR_TLBMISC: gen_helper_mmu_write_tlbmisc(cpu_env, v); break; + case CR_IPENDING: + /* ipending is read only, writes ignored. */ + break; default: tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); break; -- 2.39.5