From 8e33944f8c648e579a2827ae6f30e4d66ee87f96 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 29 Jan 2013 13:36:02 +0100 Subject: [PATCH] PPC: Unify dcbzl code path MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit The bit that makes a dcbz instruction a dcbzl instruction was declared as reserved in ppc32 ISAs. However, hardware simply ignores the bit, making code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4. Thus, mark the bit as unreserved so that we properly emulate a simple dcbz in case we're running on non-G5s. While at it, also refactor the code to check the 970 special case during runtime. This way we don't need to differenciate between a 970 dcbz and any other dcbz anymore. We also allow for future improvements to add e500mc dcbz handling. Reported-by: Amadeusz Sławiński Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 6 ++---- target-ppc/helper.h | 3 +-- target-ppc/mem_helper.c | 21 ++++++++++++--------- target-ppc/translate.c | 33 ++++++++++++--------------------- target-ppc/translate_init.c | 10 +++++----- 5 files changed, 32 insertions(+), 41 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 953146eeba3..8c081dbec51 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1857,10 +1857,8 @@ enum { PPC_CACHE = 0x0000000200000000ULL, /* icbi instruction */ PPC_CACHE_ICBI = 0x0000000400000000ULL, - /* dcbz instruction with fixed cache line size */ + /* dcbz instruction */ PPC_CACHE_DCBZ = 0x0000000800000000ULL, - /* dcbz instruction with tunable cache line size */ - PPC_CACHE_DCBZT = 0x0000001000000000ULL, /* dcba instruction */ PPC_CACHE_DCBA = 0x0000002000000000ULL, /* Freescale cache locking instructions */ @@ -1928,7 +1926,7 @@ enum { | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \ | PPC_MEM_SYNC | PPC_MEM_EIEIO \ | PPC_CACHE | PPC_CACHE_ICBI \ - | PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \ + | PPC_CACHE_DCBZ \ | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 83139d5225a..18e039452f3 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -25,8 +25,7 @@ DEF_HELPER_3(stmw, void, env, tl, i32) DEF_HELPER_4(lsw, void, env, tl, i32, i32) DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32) DEF_HELPER_4(stsw, void, env, tl, i32, i32) -DEF_HELPER_2(dcbz, void, env, tl) -DEF_HELPER_2(dcbz_970, void, env, tl) +DEF_HELPER_3(dcbz, void, env, tl, i32) DEF_HELPER_2(icbi, void, env, tl) DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32) diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c index 902b1cd8231..ba383c8f11e 100644 --- a/target-ppc/mem_helper.c +++ b/target-ppc/mem_helper.c @@ -136,18 +136,21 @@ static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size) } } -void helper_dcbz(CPUPPCState *env, target_ulong addr) +void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl) { - do_dcbz(env, addr, env->dcache_line_size); -} + int dcbz_size = env->dcache_line_size; -void helper_dcbz_970(CPUPPCState *env, target_ulong addr) -{ - if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { - do_dcbz(env, addr, 32); - } else { - do_dcbz(env, addr, env->dcache_line_size); +#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64) + if (!is_dcbzl && + (env->excp_model == POWERPC_EXCP_970) && + ((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) { + dcbz_size = 32; } +#endif + + /* XXX add e500mc support */ + + do_dcbz(env, addr, dcbz_size); } void helper_icbi(CPUPPCState *env, target_ulong addr) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 798b7acfc90..d96d1eddb73 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4118,29 +4118,21 @@ static void gen_dcbtst(DisasContext *ctx) /* dcbz */ static void gen_dcbz(DisasContext *ctx) { - TCGv t0; - gen_set_access_type(ctx, ACCESS_CACHE); - /* NIP cannot be restored if the memory exception comes from an helper */ - gen_update_nip(ctx, ctx->nip - 4); - t0 = tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - gen_helper_dcbz(cpu_env, t0); - tcg_temp_free(t0); -} + TCGv tcgv_addr; + TCGv_i32 tcgv_is_dcbzl; + int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0; -static void gen_dcbz_970(DisasContext *ctx) -{ - TCGv t0; gen_set_access_type(ctx, ACCESS_CACHE); /* NIP cannot be restored if the memory exception comes from an helper */ gen_update_nip(ctx, ctx->nip - 4); - t0 = tcg_temp_new(); - gen_addr_reg_index(ctx, t0); - if (ctx->opcode & 0x00200000) - gen_helper_dcbz(cpu_env, t0); - else - gen_helper_dcbz_970(cpu_env, t0); - tcg_temp_free(t0); + tcgv_addr = tcg_temp_new(); + tcgv_is_dcbzl = tcg_const_i32(is_dcbzl); + + gen_addr_reg_index(ctx, tcgv_addr); + gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl); + + tcg_temp_free(tcgv_addr); + tcg_temp_free_i32(tcgv_is_dcbzl); } /* dst / dstt */ @@ -8648,8 +8640,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE), GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE), -GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ), -GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT), +GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC), GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index e143af532ac..e2021c4a054 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -6298,7 +6298,7 @@ static void init_proc_7457 (CPUPPCState *env) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_STFIWX | \ - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_64B | PPC_ALTIVEC | \ @@ -6394,7 +6394,7 @@ static void init_proc_970 (CPUPPCState *env) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_STFIWX | \ - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_64B | PPC_ALTIVEC | \ @@ -6496,7 +6496,7 @@ static void init_proc_970FX (CPUPPCState *env) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_STFIWX | \ - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_64B | PPC_ALTIVEC | \ @@ -6586,7 +6586,7 @@ static void init_proc_970GX (CPUPPCState *env) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_STFIWX | \ - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_64B | PPC_ALTIVEC | \ @@ -6677,7 +6677,7 @@ static void init_proc_970MP (CPUPPCState *env) PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \ PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \ PPC_FLOAT_STFIWX | \ - PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \ + PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \ PPC_MEM_SYNC | PPC_MEM_EIEIO | \ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \ PPC_64B | PPC_ALTIVEC | \ -- 2.39.5