From 8e51559c1d1ad9ff8c787b192121e53c3d4b9f2f Mon Sep 17 00:00:00 2001 From: Sasha Levin Date: Sun, 18 Apr 2021 20:27:10 -0400 Subject: [PATCH] Fixes for 5.4 Signed-off-by: Sasha Levin --- ...-don-t-advertise-pause-in-jumbo-mode.patch | 57 ++++++ ...mance-regression-related-to-pcie-max.patch | 60 ++++++ .../r8169-improve-rtl_jumbo_config.patch | 139 +++++++++++++ ...dling-with-the-pcie-max-read-request.patch | 183 ++++++++++++++++++ ...fy-setting-pci_exp_devctl_nosnoop_en.patch | 98 ++++++++++ ...read-request-size-for-newer-chips-al.patch | 64 ++++++ queue-5.4/series | 6 + 7 files changed, 607 insertions(+) create mode 100644 queue-5.4/r8169-don-t-advertise-pause-in-jumbo-mode.patch create mode 100644 queue-5.4/r8169-fix-performance-regression-related-to-pcie-max.patch create mode 100644 queue-5.4/r8169-improve-rtl_jumbo_config.patch create mode 100644 queue-5.4/r8169-remove-fiddling-with-the-pcie-max-read-request.patch create mode 100644 queue-5.4/r8169-simplify-setting-pci_exp_devctl_nosnoop_en.patch create mode 100644 queue-5.4/r8169-tweak-max-read-request-size-for-newer-chips-al.patch diff --git a/queue-5.4/r8169-don-t-advertise-pause-in-jumbo-mode.patch b/queue-5.4/r8169-don-t-advertise-pause-in-jumbo-mode.patch new file mode 100644 index 00000000000..92d20f902be --- /dev/null +++ b/queue-5.4/r8169-don-t-advertise-pause-in-jumbo-mode.patch @@ -0,0 +1,57 @@ +From 8ff489e64e1dae53a2d9dc55e593d8f1dd9650ff Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 14 Apr 2021 10:47:10 +0200 +Subject: r8169: don't advertise pause in jumbo mode + +From: Heiner Kallweit + +[ Upstream commit 453a77894efa4d9b6ef9644d74b9419c47ac427c ] + +It has been reported [0] that using pause frames in jumbo mode impacts +performance. There's no available chip documentation, but vendor +drivers r8168 and r8125 don't advertise pause in jumbo mode. So let's +do the same, according to Roman it fixes the issue. + +[0] https://bugzilla.kernel.org/show_bug.cgi?id=212617 + +Fixes: 9cf9b84cc701 ("r8169: make use of phy_set_asym_pause") +Reported-by: Roman Mamedov +Tested-by: Roman Mamedov +Signed-off-by: Heiner Kallweit +Cc: stable@vger.kernel.org +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 9 +++++++-- + 1 file changed, 7 insertions(+), 2 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 4e4953b1433a..8ff178fc2670 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4138,6 +4138,13 @@ static void rtl_jumbo_config(struct rtl8169_private *tp) + + if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) + pcie_set_readrq(tp->pci_dev, readrq); ++ ++ /* Chip doesn't support pause in jumbo mode */ ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_Pause_BIT, ++ tp->phydev->advertising, !jumbo); ++ linkmode_mod_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, ++ tp->phydev->advertising, !jumbo); ++ phy_start_aneg(tp->phydev); + } + + DECLARE_RTL_COND(rtl_chipcmd_cond) +@@ -6314,8 +6321,6 @@ static int r8169_phy_connect(struct rtl8169_private *tp) + if (!tp->supports_gmii) + phy_set_max_speed(phydev, SPEED_100); + +- phy_support_asym_pause(phydev); +- + phy_attached_info(phydev); + + return 0; +-- +2.30.2 + diff --git a/queue-5.4/r8169-fix-performance-regression-related-to-pcie-max.patch b/queue-5.4/r8169-fix-performance-regression-related-to-pcie-max.patch new file mode 100644 index 00000000000..38337757a4a --- /dev/null +++ b/queue-5.4/r8169-fix-performance-regression-related-to-pcie-max.patch @@ -0,0 +1,60 @@ +From a0594ba9f65acd50668b0251a3ef9abbe03cf932 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Wed, 5 Feb 2020 21:22:46 +0100 +Subject: r8169: fix performance regression related to PCIe max read request + size + +From: Heiner Kallweit + +[ Upstream commit 21b5f672fb2eb1366dedc4ac9d32431146b378d3 ] + +It turned out that on low performance systems the original change can +cause lower tx performance. On a N3450-based mini-PC tx performance +in iperf3 was reduced from 950Mbps to ~900Mbps. Therefore effectively +revert the original change, just use pcie_set_readrq() now instead of +changing the PCIe capability register directly. + +Fixes: 2df49d365498 ("r8169: remove fiddling with the PCIe max read request size") +Signed-off-by: Heiner Kallweit +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 5ca28985c86b..19ebde91555d 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4099,15 +4099,18 @@ static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_12: + case RTL_GIGA_MAC_VER_17: ++ pcie_set_readrq(tp->pci_dev, 512); + r8168b_1_hw_jumbo_enable(tp); + break; + case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: ++ pcie_set_readrq(tp->pci_dev, 512); + r8168c_hw_jumbo_enable(tp); + break; + case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: + r8168dp_hw_jumbo_enable(tp); + break; + case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: ++ pcie_set_readrq(tp->pci_dev, 512); + r8168e_hw_jumbo_enable(tp); + break; + default: +@@ -4137,6 +4140,9 @@ static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) + break; + } + rtl_lock_config_regs(tp); ++ ++ if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) ++ pcie_set_readrq(tp->pci_dev, 4096); + } + + static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) +-- +2.30.2 + diff --git a/queue-5.4/r8169-improve-rtl_jumbo_config.patch b/queue-5.4/r8169-improve-rtl_jumbo_config.patch new file mode 100644 index 00000000000..ba3831e499e --- /dev/null +++ b/queue-5.4/r8169-improve-rtl_jumbo_config.patch @@ -0,0 +1,139 @@ +From 6a5bb02bd30a6dcfa8ffd62b27f337f3891ca057 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 15 Feb 2020 14:52:58 +0100 +Subject: r8169: improve rtl_jumbo_config + +From: Heiner Kallweit + +[ Upstream commit 9db0ac57bd3286fedcf43a86b29b847cea281cc7 ] + +Merge enabling and disabling jumbo packets to one function to make +the code a little simpler. + +Signed-off-by: Heiner Kallweit +Signed-off-by: David S. Miller +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 69 +++++++++-------------- + 1 file changed, 27 insertions(+), 42 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 19ebde91555d..1352dd0b69e9 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4093,66 +4093,52 @@ static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) + RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); + } + +-static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) ++static void rtl_jumbo_config(struct rtl8169_private *tp) + { +- rtl_unlock_config_regs(tp); +- switch (tp->mac_version) { +- case RTL_GIGA_MAC_VER_12: +- case RTL_GIGA_MAC_VER_17: +- pcie_set_readrq(tp->pci_dev, 512); +- r8168b_1_hw_jumbo_enable(tp); +- break; +- case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: +- pcie_set_readrq(tp->pci_dev, 512); +- r8168c_hw_jumbo_enable(tp); +- break; +- case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: +- r8168dp_hw_jumbo_enable(tp); +- break; +- case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: +- pcie_set_readrq(tp->pci_dev, 512); +- r8168e_hw_jumbo_enable(tp); +- break; +- default: +- break; +- } +- rtl_lock_config_regs(tp); +-} ++ bool jumbo = tp->dev->mtu > ETH_DATA_LEN; + +-static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) +-{ + rtl_unlock_config_regs(tp); + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_12: + case RTL_GIGA_MAC_VER_17: +- r8168b_1_hw_jumbo_disable(tp); ++ if (jumbo) { ++ pcie_set_readrq(tp->pci_dev, 512); ++ r8168b_1_hw_jumbo_enable(tp); ++ } else { ++ r8168b_1_hw_jumbo_disable(tp); ++ } + break; + case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: +- r8168c_hw_jumbo_disable(tp); ++ if (jumbo) { ++ pcie_set_readrq(tp->pci_dev, 512); ++ r8168c_hw_jumbo_enable(tp); ++ } else { ++ r8168c_hw_jumbo_disable(tp); ++ } + break; + case RTL_GIGA_MAC_VER_27 ... RTL_GIGA_MAC_VER_28: +- r8168dp_hw_jumbo_disable(tp); ++ if (jumbo) ++ r8168dp_hw_jumbo_enable(tp); ++ else ++ r8168dp_hw_jumbo_disable(tp); + break; + case RTL_GIGA_MAC_VER_31 ... RTL_GIGA_MAC_VER_33: +- r8168e_hw_jumbo_disable(tp); ++ if (jumbo) { ++ pcie_set_readrq(tp->pci_dev, 512); ++ r8168e_hw_jumbo_enable(tp); ++ } else { ++ r8168e_hw_jumbo_disable(tp); ++ } + break; + default: + break; + } + rtl_lock_config_regs(tp); + +- if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) ++ if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) + pcie_set_readrq(tp->pci_dev, 4096); + } + +-static void rtl_jumbo_config(struct rtl8169_private *tp, int mtu) +-{ +- if (mtu > ETH_DATA_LEN) +- rtl_hw_jumbo_enable(tp); +- else +- rtl_hw_jumbo_disable(tp); +-} +- + DECLARE_RTL_COND(rtl_chipcmd_cond) + { + return RTL_R8(tp, ChipCmd) & CmdReset; +@@ -5458,7 +5444,7 @@ static void rtl_hw_start(struct rtl8169_private *tp) + rtl_set_rx_tx_desc_registers(tp); + rtl_lock_config_regs(tp); + +- rtl_jumbo_config(tp, tp->dev->mtu); ++ rtl_jumbo_config(tp); + + /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ + RTL_R16(tp, CPlusCmd); +@@ -5473,10 +5459,9 @@ static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) + { + struct rtl8169_private *tp = netdev_priv(dev); + +- rtl_jumbo_config(tp, new_mtu); +- + dev->mtu = new_mtu; + netdev_update_features(dev); ++ rtl_jumbo_config(tp); + + /* Reportedly at least Asus X453MA truncates packets otherwise */ + if (tp->mac_version == RTL_GIGA_MAC_VER_37) +-- +2.30.2 + diff --git a/queue-5.4/r8169-remove-fiddling-with-the-pcie-max-read-request.patch b/queue-5.4/r8169-remove-fiddling-with-the-pcie-max-read-request.patch new file mode 100644 index 00000000000..0e8bdabc302 --- /dev/null +++ b/queue-5.4/r8169-remove-fiddling-with-the-pcie-max-read-request.patch @@ -0,0 +1,183 @@ +From 064490ecd4f5f77d2d36b1e03ef70adb473ebe0e Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 21 Oct 2019 21:22:07 +0200 +Subject: r8169: remove fiddling with the PCIe max read request size + +From: Heiner Kallweit + +[ Upstream commit 2df49d36549808a7357ad9f78b7a8e39516e7809 ] + +The attempt to improve performance by changing the PCIe max read request +size was added in the vendor driver more than 10 years back and copied +to r8169 driver. In the vendor driver this has been removed long ago. +Obviously it had no effect, also in my tests I didn't see any +difference. Typically the max payload size is less than 512 bytes +anyway, and the PCI core takes care that the maximum supported value +is set. So let's remove fiddling with PCIe max read request size from +r8169 too. + +Signed-off-by: Heiner Kallweit +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 40 +++-------------------- + 1 file changed, 4 insertions(+), 36 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index bd8decc54b87..fb11561a4f17 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -742,12 +742,6 @@ static void rtl_unlock_config_regs(struct rtl8169_private *tp) + RTL_W8(tp, Cfg9346, Cfg9346_Unlock); + } + +-static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force) +-{ +- pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL, +- PCI_EXP_DEVCTL_READRQ, force); +-} +- + static bool rtl_is_8125(struct rtl8169_private *tp) + { + return tp->mac_version >= RTL_GIGA_MAC_VER_60; +@@ -4057,14 +4051,12 @@ static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp) + { + RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); + RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); + } + + static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp) + { + RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); + RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); + } + + static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp) +@@ -4082,7 +4074,6 @@ static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp) + RTL_W8(tp, MaxTxPacketSize, 0x24); + RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); + RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B); + } + + static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) +@@ -4090,19 +4081,18 @@ static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) + RTL_W8(tp, MaxTxPacketSize, 0x3f); + RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); + RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); + } + + static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) + { +- rtl_tx_performance_tweak(tp, +- PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN); ++ pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, ++ PCI_EXP_DEVCTL_NOSNOOP_EN); + } + + static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) + { +- rtl_tx_performance_tweak(tp, +- PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN); ++ pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, ++ PCI_EXP_DEVCTL_NOSNOOP_EN); + } + + static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) +@@ -4575,18 +4565,12 @@ static void rtl_hw_start_8168d(struct rtl8169_private *tp) + rtl_set_def_aspm_entry_latency(tp); + + rtl_disable_clock_request(tp); +- +- if (tp->dev->mtu <= ETH_DATA_LEN) +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); + } + + static void rtl_hw_start_8168dp(struct rtl8169_private *tp) + { + rtl_set_def_aspm_entry_latency(tp); + +- if (tp->dev->mtu <= ETH_DATA_LEN) +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + rtl_disable_clock_request(tp); + } + +@@ -4601,8 +4585,6 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp) + + rtl_set_def_aspm_entry_latency(tp); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + rtl_ephy_init(tp, e_info_8168d_4); + + rtl_enable_clock_request(tp); +@@ -4677,8 +4659,6 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp) + { + rtl_set_def_aspm_entry_latency(tp); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); + rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); + rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); +@@ -4741,8 +4721,6 @@ static void rtl_hw_start_8168g(struct rtl8169_private *tp) + + rtl_set_def_aspm_entry_latency(tp); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + rtl_reset_packet_filter(tp); + rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); + +@@ -4979,8 +4957,6 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) + + rtl_set_def_aspm_entry_latency(tp); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + rtl_reset_packet_filter(tp); + + rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4)); +@@ -5038,8 +5014,6 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp) + + rtl_set_def_aspm_entry_latency(tp); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + rtl_reset_packet_filter(tp); + + rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80); +@@ -5142,8 +5116,6 @@ static void rtl_hw_start_8102e_1(struct rtl8169_private *tp) + + RTL_W8(tp, DBG_REG, FIX_NAK_1); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + RTL_W8(tp, Config1, + LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); + RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); +@@ -5159,8 +5131,6 @@ static void rtl_hw_start_8102e_2(struct rtl8169_private *tp) + { + rtl_set_def_aspm_entry_latency(tp); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable); + RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); + } +@@ -5221,8 +5191,6 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp) + + rtl_ephy_init(tp, e_info_8402); + +- rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B); +- + rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); + rtl_reset_packet_filter(tp); + rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); +-- +2.30.2 + diff --git a/queue-5.4/r8169-simplify-setting-pci_exp_devctl_nosnoop_en.patch b/queue-5.4/r8169-simplify-setting-pci_exp_devctl_nosnoop_en.patch new file mode 100644 index 00000000000..2facbd14ca8 --- /dev/null +++ b/queue-5.4/r8169-simplify-setting-pci_exp_devctl_nosnoop_en.patch @@ -0,0 +1,98 @@ +From 3dcbf79506ad21892a0ae8af0261b57ae5862e92 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 21 Oct 2019 21:22:42 +0200 +Subject: r8169: simplify setting PCI_EXP_DEVCTL_NOSNOOP_EN + +From: Heiner Kallweit + +[ Upstream commit e0bbe7cbb3c5ff72d680993edf89db2391e80d5d ] + +r8168b_0_hw_jumbo_enable() and r8168b_0_hw_jumbo_disable() both do the +same and just set PCI_EXP_DEVCTL_NOSNOOP_EN. We can simplify the code +by moving this setting for RTL8168B to rtl_hw_start_8168(). + +Signed-off-by: Heiner Kallweit +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 34 +++++++---------------- + 1 file changed, 10 insertions(+), 24 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index fb11561a4f17..5ca28985c86b 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4083,29 +4083,13 @@ static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp) + RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); + } + +-static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp) +-{ +- pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, +- PCI_EXP_DEVCTL_NOSNOOP_EN); +-} +- +-static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp) +-{ +- pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, +- PCI_EXP_DEVCTL_NOSNOOP_EN); +-} +- + static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp) + { +- r8168b_0_hw_jumbo_enable(tp); +- + RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); + } + + static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) + { +- r8168b_0_hw_jumbo_disable(tp); +- + RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); + } + +@@ -4113,9 +4097,6 @@ static void rtl_hw_jumbo_enable(struct rtl8169_private *tp) + { + rtl_unlock_config_regs(tp); + switch (tp->mac_version) { +- case RTL_GIGA_MAC_VER_11: +- r8168b_0_hw_jumbo_enable(tp); +- break; + case RTL_GIGA_MAC_VER_12: + case RTL_GIGA_MAC_VER_17: + r8168b_1_hw_jumbo_enable(tp); +@@ -4139,9 +4120,6 @@ static void rtl_hw_jumbo_disable(struct rtl8169_private *tp) + { + rtl_unlock_config_regs(tp); + switch (tp->mac_version) { +- case RTL_GIGA_MAC_VER_11: +- r8168b_0_hw_jumbo_disable(tp); +- break; + case RTL_GIGA_MAC_VER_12: + case RTL_GIGA_MAC_VER_17: + r8168b_1_hw_jumbo_disable(tp); +@@ -5406,10 +5384,18 @@ static void rtl_hw_start_8125(struct rtl8169_private *tp) + + static void rtl_hw_start_8168(struct rtl8169_private *tp) + { +- if (tp->mac_version == RTL_GIGA_MAC_VER_13 || +- tp->mac_version == RTL_GIGA_MAC_VER_16) ++ switch (tp->mac_version) { ++ case RTL_GIGA_MAC_VER_11: ++ case RTL_GIGA_MAC_VER_12: ++ case RTL_GIGA_MAC_VER_13: ++ case RTL_GIGA_MAC_VER_16: ++ case RTL_GIGA_MAC_VER_17: + pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_NOSNOOP_EN); ++ break; ++ default: ++ break; ++ } + + if (rtl_is_8168evl_up(tp)) + RTL_W8(tp, MaxTxPacketSize, EarlySize); +-- +2.30.2 + diff --git a/queue-5.4/r8169-tweak-max-read-request-size-for-newer-chips-al.patch b/queue-5.4/r8169-tweak-max-read-request-size-for-newer-chips-al.patch new file mode 100644 index 00000000000..9a1c627c11b --- /dev/null +++ b/queue-5.4/r8169-tweak-max-read-request-size-for-newer-chips-al.patch @@ -0,0 +1,64 @@ +From 47f8b895e6b35aa6af489711ee6f1416e742fcf5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Sat, 9 Jan 2021 23:01:18 +0100 +Subject: r8169: tweak max read request size for newer chips also in jumbo mtu + mode + +From: Heiner Kallweit + +[ Upstream commit 5e00e16cb98935bcf06f51931876d898c226f65c ] + +So far we don't increase the max read request size if we switch to +jumbo mode before bringing up the interface for the first time. +Let's change this. + +Signed-off-by: Heiner Kallweit +Signed-off-by: Jakub Kicinski +Signed-off-by: Sasha Levin +--- + drivers/net/ethernet/realtek/r8169_main.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c +index 1352dd0b69e9..4e4953b1433a 100644 +--- a/drivers/net/ethernet/realtek/r8169_main.c ++++ b/drivers/net/ethernet/realtek/r8169_main.c +@@ -4096,13 +4096,14 @@ static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp) + static void rtl_jumbo_config(struct rtl8169_private *tp) + { + bool jumbo = tp->dev->mtu > ETH_DATA_LEN; ++ int readrq = 4096; + + rtl_unlock_config_regs(tp); + switch (tp->mac_version) { + case RTL_GIGA_MAC_VER_12: + case RTL_GIGA_MAC_VER_17: + if (jumbo) { +- pcie_set_readrq(tp->pci_dev, 512); ++ readrq = 512; + r8168b_1_hw_jumbo_enable(tp); + } else { + r8168b_1_hw_jumbo_disable(tp); +@@ -4110,7 +4111,7 @@ static void rtl_jumbo_config(struct rtl8169_private *tp) + break; + case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_26: + if (jumbo) { +- pcie_set_readrq(tp->pci_dev, 512); ++ readrq = 512; + r8168c_hw_jumbo_enable(tp); + } else { + r8168c_hw_jumbo_disable(tp); +@@ -4135,8 +4136,8 @@ static void rtl_jumbo_config(struct rtl8169_private *tp) + } + rtl_lock_config_regs(tp); + +- if (!jumbo && pci_is_pcie(tp->pci_dev) && tp->supports_gmii) +- pcie_set_readrq(tp->pci_dev, 4096); ++ if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii) ++ pcie_set_readrq(tp->pci_dev, readrq); + } + + DECLARE_RTL_COND(rtl_chipcmd_cond) +-- +2.30.2 + diff --git a/queue-5.4/series b/queue-5.4/series index 47def80bb55..8d879b7acdd 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -63,3 +63,9 @@ ibmvnic-remove-duplicate-napi_schedule-call-in-open-function.patch gro-ensure-frag0-meets-ip-header-alignment.patch arm-footbridge-fix-pci-interrupt-mapping.patch arm64-dts-allwinner-fix-sd-card-cd-gpio-for-sopine-s.patch +r8169-remove-fiddling-with-the-pcie-max-read-request.patch +r8169-simplify-setting-pci_exp_devctl_nosnoop_en.patch +r8169-fix-performance-regression-related-to-pcie-max.patch +r8169-improve-rtl_jumbo_config.patch +r8169-tweak-max-read-request-size-for-newer-chips-al.patch +r8169-don-t-advertise-pause-in-jumbo-mode.patch -- 2.47.3