From 8fb00a521c7f23f6d0f2687e8b521db8ac7dc49e Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Wed, 26 Oct 2022 12:52:22 +0200 Subject: [PATCH] 5.15-stable patches added patches: arm64-mm-consolidate-tcr_el1-fields.patch --- .../arm64-mm-consolidate-tcr_el1-fields.patch | 64 +++++++++++++++++++ queue-5.15/series | 1 + 2 files changed, 65 insertions(+) create mode 100644 queue-5.15/arm64-mm-consolidate-tcr_el1-fields.patch diff --git a/queue-5.15/arm64-mm-consolidate-tcr_el1-fields.patch b/queue-5.15/arm64-mm-consolidate-tcr_el1-fields.patch new file mode 100644 index 00000000000..6759342084b --- /dev/null +++ b/queue-5.15/arm64-mm-consolidate-tcr_el1-fields.patch @@ -0,0 +1,64 @@ +From e921da6bc7cac5f0e8458fe5df18ae08eb538f54 Mon Sep 17 00:00:00 2001 +From: Anshuman Khandual +Date: Tue, 25 Jan 2022 20:08:33 +0530 +Subject: arm64/mm: Consolidate TCR_EL1 fields + +From: Anshuman Khandual + +commit e921da6bc7cac5f0e8458fe5df18ae08eb538f54 upstream. + +This renames and moves SYS_TCR_EL1_TCMA1 and SYS_TCR_EL1_TCMA0 definitions +into pgtable-hwdef.h thus consolidating all TCR fields in a single header. +This does not cause any functional change. + +Cc: Catalin Marinas +Cc: Will Deacon +Cc: linux-arm-kernel@lists.infradead.org +Cc: linux-kernel@vger.kernel.org +Acked-by: Catalin Marinas +Signed-off-by: Anshuman Khandual +Link: https://lore.kernel.org/r/1643121513-21854-1-git-send-email-anshuman.khandual@arm.com +Signed-off-by: Will Deacon +Cc: Evgenii Stepanov +Signed-off-by: Greg Kroah-Hartman +--- + arch/arm64/include/asm/pgtable-hwdef.h | 2 ++ + arch/arm64/include/asm/sysreg.h | 4 ---- + arch/arm64/mm/proc.S | 2 +- + 3 files changed, 3 insertions(+), 5 deletions(-) + +--- a/arch/arm64/include/asm/pgtable-hwdef.h ++++ b/arch/arm64/include/asm/pgtable-hwdef.h +@@ -273,6 +273,8 @@ + #define TCR_NFD1 (UL(1) << 54) + #define TCR_E0PD0 (UL(1) << 55) + #define TCR_E0PD1 (UL(1) << 56) ++#define TCR_TCMA0 (UL(1) << 57) ++#define TCR_TCMA1 (UL(1) << 58) + + /* + * TTBR. +--- a/arch/arm64/include/asm/sysreg.h ++++ b/arch/arm64/include/asm/sysreg.h +@@ -1094,10 +1094,6 @@ + #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ + #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) + +-/* TCR EL1 Bit Definitions */ +-#define SYS_TCR_EL1_TCMA1 (BIT(58)) +-#define SYS_TCR_EL1_TCMA0 (BIT(57)) +- + /* GCR_EL1 Definitions */ + #define SYS_GCR_EL1_RRND (BIT(16)) + #define SYS_GCR_EL1_EXCL_MASK 0xffffUL +--- a/arch/arm64/mm/proc.S ++++ b/arch/arm64/mm/proc.S +@@ -46,7 +46,7 @@ + #endif + + #ifdef CONFIG_KASAN_HW_TAGS +-#define TCR_MTE_FLAGS SYS_TCR_EL1_TCMA1 | TCR_TBI1 | TCR_TBID1 ++#define TCR_MTE_FLAGS TCR_TCMA1 | TCR_TBI1 | TCR_TBID1 + #else + /* + * The mte_zero_clear_page_tags() implementation uses DC GZVA, which relies on diff --git a/queue-5.15/series b/queue-5.15/series index a06907bf49a..dc4515ead95 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -1 +1,2 @@ r8152-add-pid-for-the-lenovo-onelink-dock.patch +arm64-mm-consolidate-tcr_el1-fields.patch -- 2.47.3