From 909a7cd0f6502e5b8b836c654262a133ec174359 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 20 Oct 2024 11:23:03 +0200 Subject: [PATCH] fix up x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch --- .../x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch | 2 +- .../x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch | 2 +- queue-6.1/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch | 2 +- queue-6.6/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/queue-5.10/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch b/queue-5.10/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch index 28d72d5689d..10b226f4a39 100644 --- a/queue-5.10/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch +++ b/queue-5.10/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch @@ -40,7 +40,7 @@ Signed-off-by: Greg Kroah-Hartman #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ -+#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ ++#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* "" IBPB clears return address predictor */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/queue-5.15/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch b/queue-5.15/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch index e3b43269eef..389c95059f7 100644 --- a/queue-5.15/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch +++ b/queue-5.15/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch @@ -40,7 +40,7 @@ Signed-off-by: Greg Kroah-Hartman #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ -+#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ ++#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* "" IBPB clears return address predictor */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ diff --git a/queue-6.1/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch b/queue-6.1/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch index 4b778af595c..3bd597a019a 100644 --- a/queue-6.1/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch +++ b/queue-6.1/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch @@ -40,7 +40,7 @@ Signed-off-by: Greg Kroah-Hartman #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ -+#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ ++#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* "" IBPB clears return address predictor */ #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ diff --git a/queue-6.6/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch b/queue-6.6/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch index 916760038c2..04e724730a9 100644 --- a/queue-6.6/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch +++ b/queue-6.6/x86-cpufeatures-define-x86_feature_amd_ibpb_ret.patch @@ -40,7 +40,7 @@ Signed-off-by: Greg Kroah-Hartman #define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */ #define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */ #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */ -+#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */ ++#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* "" IBPB clears return address predictor */ #define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ -- 2.47.3