From 928954fe58e69767b138816ab58e1a7e48f2c685 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 15 Nov 2017 13:14:51 +0100 Subject: [PATCH] dm: misc: bind STM32F4/F7 clock from rcc MFD driver Like STM32H7, now STM32F4/F7 clock drivers are binded by MFD stm32_rcc driver. This also allows to add reset support to STM32F4/F7 SoCs family. As Reset driver is not part of SPL supported drivers, don't bind it in case of SPL to avoid that stm32_rcc_bind() returns an error. Signed-off-by: Patrice Chotard Reviewed-by: Vikas Manocha --- drivers/clk/clk_stm32f.c | 54 ++++++++++------------------------------ drivers/misc/stm32_rcc.c | 42 +++++++++++++++++++++++++++---- include/stm32_rcc.h | 52 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+), 46 deletions(-) create mode 100644 include/stm32_rcc.h diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index c7af7a1d8d..6e29c55e0a 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -71,38 +72,6 @@ */ #define RCC_APB2ENR_SYSCFGEN BIT(14) - -struct pll_psc { - u8 pll_m; - u16 pll_n; - u8 pll_p; - u8 pll_q; - u8 ahb_psc; - u8 apb1_psc; - u8 apb2_psc; -}; - -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF - -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 - -struct stm32_clk_info { - struct pll_psc sys_pll_psc; - bool has_overdrive; -}; - struct stm32_clk_info stm32f4_clk_info = { /* 180 MHz */ .sys_pll_psc = { @@ -311,7 +280,17 @@ static int stm32_clk_probe(struct udevice *dev) return -EINVAL; priv->base = (struct stm32_rcc_regs *)addr; - priv->info = (struct stm32_clk_info *)dev_get_driver_data(dev); + + switch (dev_get_driver_data(dev)) { + case STM32F4: + priv->info = &stm32f4_clk_info; + break; + case STM32F7: + priv->info = &stm32f7_clk_info; + break; + default: + return -EINVAL; + } if (priv->info->has_overdrive) { err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, @@ -353,16 +332,9 @@ static struct clk_ops stm32_clk_ops = { .get_rate = stm32_clk_get_rate, }; -static const struct udevice_id stm32_clk_ids[] = { - { .compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32f4_clk_info}, - { .compatible = "st,stm32f746-rcc", .data = (ulong)&stm32f7_clk_info}, - {} -}; - U_BOOT_DRIVER(stm32fx_clk) = { - .name = "stm32fx_clk", + .name = "stm32fx_rcc_clock", .id = UCLASS_CLK, - .of_match = stm32_clk_ids, .ops = &stm32_clk_ops, .probe = stm32_clk_probe, .priv_auto_alloc_size = sizeof(struct stm32_clk), diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index 32d39719d8..87d9928362 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -8,31 +8,63 @@ #include #include #include +#include +#include #include +struct stm32_rcc_clk stm32_rcc_clk_f4 = { + .drv_name = "stm32fx_rcc_clock", + .soc = STM32F4, +}; + +struct stm32_rcc_clk stm32_rcc_clk_f7 = { + .drv_name = "stm32fx_rcc_clock", + .soc = STM32F7, +}; + +struct stm32_rcc_clk stm32_rcc_clk_h7 = { + .drv_name = "stm32h7_rcc_clock", +}; + static int stm32_rcc_bind(struct udevice *dev) { - int ret; struct udevice *child; + struct driver *drv; + struct stm32_rcc_clk *rcc_clk = + (struct stm32_rcc_clk *)dev_get_driver_data(dev); + int ret; debug("%s(dev=%p)\n", __func__, dev); - ret = device_bind_driver_to_node(dev, "stm32h7_rcc_clock", - "stm32h7_rcc_clock", - dev_ofnode(dev), &child); + drv = lists_driver_lookup_name(rcc_clk->drv_name); + if (!drv) { + debug("Cannot find driver '%s'\n", rcc_clk->drv_name); + return -ENOENT; + } + + ret = device_bind_with_driver_data(dev, drv, rcc_clk->drv_name, + rcc_clk->soc, + dev_ofnode(dev), &child); + if (ret) return ret; +#ifdef CONFIG_SPL_BUILD + return 0; +#else return device_bind_driver_to_node(dev, "stm32_rcc_reset", "stm32_rcc_reset", dev_ofnode(dev), &child); +#endif } static const struct misc_ops stm32_rcc_ops = { }; static const struct udevice_id stm32_rcc_ids[] = { - {.compatible = "st,stm32h743-rcc"}, + {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f4 }, + {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 }, + {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 }, { } }; diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h new file mode 100644 index 0000000000..6dfb9cc257 --- /dev/null +++ b/include/stm32_rcc.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __STM32_RCC_H_ +#define __STM32_RCC_H_ + +#define AHB_PSC_1 0 +#define AHB_PSC_2 0x8 +#define AHB_PSC_4 0x9 +#define AHB_PSC_8 0xA +#define AHB_PSC_16 0xB +#define AHB_PSC_64 0xC +#define AHB_PSC_128 0xD +#define AHB_PSC_256 0xE +#define AHB_PSC_512 0xF + +#define APB_PSC_1 0 +#define APB_PSC_2 0x4 +#define APB_PSC_4 0x5 +#define APB_PSC_8 0x6 +#define APB_PSC_16 0x7 + +struct pll_psc { + u8 pll_m; + u16 pll_n; + u8 pll_p; + u8 pll_q; + u8 ahb_psc; + u8 apb1_psc; + u8 apb2_psc; +}; + +struct stm32_clk_info { + struct pll_psc sys_pll_psc; + bool has_overdrive; +}; + +enum soc_family { + STM32F4, + STM32F7, +}; + +struct stm32_rcc_clk { + char *drv_name; + enum soc_family soc; +}; + +#endif /* __STM32_RCC_H_ */ -- 2.39.2