From 94f6bdf89a0db0e5aa1f8919644b24f9efb33e8c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 10 Mar 2025 17:09:58 +0100 Subject: [PATCH] 5.10-stable patches added patches: x86-mm-don-t-disable-pcid-when-invlpg-has-been-fixed-by-microcode.patch --- ...n-invlpg-has-been-fixed-by-microcode.patch | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 queue-5.10/x86-mm-don-t-disable-pcid-when-invlpg-has-been-fixed-by-microcode.patch diff --git a/queue-5.10/x86-mm-don-t-disable-pcid-when-invlpg-has-been-fixed-by-microcode.patch b/queue-5.10/x86-mm-don-t-disable-pcid-when-invlpg-has-been-fixed-by-microcode.patch new file mode 100644 index 0000000000..febdf98355 --- /dev/null +++ b/queue-5.10/x86-mm-don-t-disable-pcid-when-invlpg-has-been-fixed-by-microcode.patch @@ -0,0 +1,79 @@ +From f24f669d03f884a6ef95cca84317d0f329e93961 Mon Sep 17 00:00:00 2001 +From: Xi Ruoyao +Date: Wed, 22 May 2024 10:06:24 +0800 +Subject: x86/mm: Don't disable PCID when INVLPG has been fixed by microcode + +From: Xi Ruoyao + +commit f24f669d03f884a6ef95cca84317d0f329e93961 upstream. + +Per the "Processor Specification Update" documentations referred by +the intel-microcode-20240312 release note, this microcode release has +fixed the issue for all affected models. + +So don't disable PCID if the microcode is new enough. The precise +minimum microcode revision fixing the issue was provided by Pawan +Intel. + +[ dhansen: comment and changelog tweaks ] + +Signed-off-by: Xi Ruoyao +Signed-off-by: Dave Hansen +Acked-by: Pawan Gupta +Link: https://lore.kernel.org/all/168436059559.404.13934972543631851306.tip-bot2@tip-bot2/ +Link: https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20240312 +Link: https://cdrdv2.intel.com/v1/dl/getContent/740518 # RPL042, rev. 13 +Link: https://cdrdv2.intel.com/v1/dl/getContent/682436 # ADL063, rev. 24 +Link: https://lore.kernel.org/all/20240325231300.qrltbzf6twm43ftb@desk/ +Link: https://lore.kernel.org/all/20240522020625.69418-1-xry111%40xry111.site +Signed-off-by: Pawan Gupta +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/mm/init.c | 23 ++++++++++++++--------- + 1 file changed, 14 insertions(+), 9 deletions(-) + +--- a/arch/x86/mm/init.c ++++ b/arch/x86/mm/init.c +@@ -258,28 +258,33 @@ static void __init probe_page_size_mask( + } + + /* +- * INVLPG may not properly flush Global entries +- * on these CPUs when PCIDs are enabled. ++ * INVLPG may not properly flush Global entries on ++ * these CPUs. New microcode fixes the issue. + */ + static const struct x86_cpu_id invlpg_miss_ids[] = { +- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0), +- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0), +- X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, 0), +- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0), +- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0), +- X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0), ++ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, 0x2e), ++ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 0x42c), ++ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N, 0x11), ++ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE, 0x118), ++ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P, 0x4117), ++ X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S, 0x2e), + {} + }; + + static void setup_pcid(void) + { ++ const struct x86_cpu_id *invlpg_miss_match; ++ + if (!IS_ENABLED(CONFIG_X86_64)) + return; + + if (!boot_cpu_has(X86_FEATURE_PCID)) + return; + +- if (x86_match_cpu(invlpg_miss_ids)) { ++ invlpg_miss_match = x86_match_cpu(invlpg_miss_ids); ++ ++ if (invlpg_miss_match && ++ boot_cpu_data.microcode < invlpg_miss_match->driver_data) { + pr_info("Incomplete global flushes, disabling PCID"); + setup_clear_cpu_cap(X86_FEATURE_PCID); + return; -- 2.47.2