From 955fd0ad5d610f62ba2f4ce46a872bf50434dcf8 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Tue, 15 Aug 2017 07:57:12 -0700 Subject: [PATCH] target/arm: Correct exclusive store cmpxchg memop mask MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit When we perform the atomic_cmpxchg operation we want to perform the operation on a pair of 32-bit registers. Previously we were just passing the register size in which was set to MO_32. This would result in the high register to be ignored. To fix this issue we hardcode the size to be 64-bits long when operating on 32-bit pairs. Reviewed-by: Edgar E. Iglesias Tested-by: Portia Stephens Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Alistair Francis Signed-off-by: Richard Henderson Message-id: 20170815145714.17635-2-richard.henderson@linaro.org Message-Id: Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 58ed4c6d057..113e2e172bf 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high); tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp, get_mem_index(s), - size | MO_ALIGN | s->be_data); + MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val); tcg_temp_free_i64(val); } else if (s->be_data == MO_LE) { -- 2.39.5