From 96393b7a662e1a7f25522e8088b0a9670eb56136 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 8 Jul 2019 14:44:09 +0200 Subject: [PATCH] 4.9-stable patches added patches: dmaengine-imx-sdma-remove-bd_intr-for-channel0.patch mips-add-missing-ehb-in-mtc0-mfc0-sequence.patch --- ...imx-sdma-remove-bd_intr-for-channel0.patch | 54 ++++++++ ...dd-missing-ehb-in-mtc0-mfc0-sequence.patch | 127 ++++++++++++++++++ queue-4.9/series | 2 + 3 files changed, 183 insertions(+) create mode 100644 queue-4.9/dmaengine-imx-sdma-remove-bd_intr-for-channel0.patch create mode 100644 queue-4.9/mips-add-missing-ehb-in-mtc0-mfc0-sequence.patch diff --git a/queue-4.9/dmaengine-imx-sdma-remove-bd_intr-for-channel0.patch b/queue-4.9/dmaengine-imx-sdma-remove-bd_intr-for-channel0.patch new file mode 100644 index 00000000000..2eacd161116 --- /dev/null +++ b/queue-4.9/dmaengine-imx-sdma-remove-bd_intr-for-channel0.patch @@ -0,0 +1,54 @@ +From 3f93a4f297961c12bb17aa16cb3a4d1291823cae Mon Sep 17 00:00:00 2001 +From: Robin Gong +Date: Fri, 21 Jun 2019 16:23:06 +0800 +Subject: dmaengine: imx-sdma: remove BD_INTR for channel0 + +From: Robin Gong + +commit 3f93a4f297961c12bb17aa16cb3a4d1291823cae upstream. + +It is possible for an irq triggered by channel0 to be received later +after clks are disabled once firmware loaded during sdma probe. If +that happens then clearing them by writing to SDMA_H_INTR won't work +and the kernel will hang processing infinite interrupts. Actually, +don't need interrupt triggered on channel0 since it's pollling +SDMA_H_STATSTOP to know channel0 done rather than interrupt in +current code, just clear BD_INTR to disable channel0 interrupt to +avoid the above case. +This issue was brought by commit 1d069bfa3c78 ("dmaengine: imx-sdma: +ack channel 0 IRQ in the interrupt handler") which didn't take care +the above case. + +Fixes: 1d069bfa3c78 ("dmaengine: imx-sdma: ack channel 0 IRQ in the interrupt handler") +Cc: stable@vger.kernel.org #5.0+ +Signed-off-by: Robin Gong +Reported-by: Sven Van Asbroeck +Tested-by: Sven Van Asbroeck +Reviewed-by: Michael Olbrich +Signed-off-by: Vinod Koul +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/dma/imx-sdma.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/dma/imx-sdma.c ++++ b/drivers/dma/imx-sdma.c +@@ -632,7 +632,7 @@ static int sdma_load_script(struct sdma_ + spin_lock_irqsave(&sdma->channel_0_lock, flags); + + bd0->mode.command = C0_SETPM; +- bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; ++ bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; + bd0->mode.count = size / 2; + bd0->buffer_addr = buf_phys; + bd0->ext_buffer_addr = address; +@@ -909,7 +909,7 @@ static int sdma_load_context(struct sdma + context->gReg[7] = sdmac->watermark_level; + + bd0->mode.command = C0_SETDM; +- bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD; ++ bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; + bd0->mode.count = sizeof(*context) / 4; + bd0->buffer_addr = sdma->context_phys; + bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; diff --git a/queue-4.9/mips-add-missing-ehb-in-mtc0-mfc0-sequence.patch b/queue-4.9/mips-add-missing-ehb-in-mtc0-mfc0-sequence.patch new file mode 100644 index 00000000000..86ad36dcdec --- /dev/null +++ b/queue-4.9/mips-add-missing-ehb-in-mtc0-mfc0-sequence.patch @@ -0,0 +1,127 @@ +From 0b24cae4d535045f4c9e177aa228d4e97bad212c Mon Sep 17 00:00:00 2001 +From: Dmitry Korotin +Date: Mon, 24 Jun 2019 19:05:27 +0000 +Subject: MIPS: Add missing EHB in mtc0 -> mfc0 sequence. + +From: Dmitry Korotin + +commit 0b24cae4d535045f4c9e177aa228d4e97bad212c upstream. + +Add a missing EHB (Execution Hazard Barrier) in mtc0 -> mfc0 sequence. +Without this execution hazard barrier it's possible for the value read +back from the KScratch register to be the value from before the mtc0. + +Reproducible on P5600 & P6600. + +The hazard is documented in the MIPS Architecture Reference Manual Vol. +III: MIPS32/microMIPS32 Privileged Resource Architecture (MD00088), rev +6.03 table 8.1 which includes: + + Producer | Consumer | Hazard + ----------|----------|---------------------------- + mtc0 | mfc0 | any coprocessor 0 register + +Signed-off-by: Dmitry Korotin +[paul.burton@mips.com: + - Commit message tweaks. + - Add Fixes tags. + - Mark for stable back to v3.15 where P5600 support was introduced.] +Signed-off-by: Paul Burton +Fixes: 3d8bfdd03072 ("MIPS: Use C0_KScratch (if present) to hold PGD pointer.") +Fixes: 829dcc0a956a ("MIPS: Add MIPS P5600 probe support") +Cc: linux-mips@vger.kernel.org +Cc: stable@vger.kernel.org # v3.15+ +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/mm/tlbex.c | 29 ++++++++++++++++++++--------- + 1 file changed, 20 insertions(+), 9 deletions(-) + +--- a/arch/mips/mm/tlbex.c ++++ b/arch/mips/mm/tlbex.c +@@ -386,6 +386,7 @@ static struct work_registers build_get_w + static void build_restore_work_registers(u32 **p) + { + if (scratch_reg >= 0) { ++ uasm_i_ehb(p); + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); + return; + } +@@ -674,10 +675,12 @@ static void build_restore_pagemask(u32 * + uasm_i_mtc0(p, 0, C0_PAGEMASK); + uasm_il_b(p, r, lid); + } +- if (scratch_reg >= 0) ++ if (scratch_reg >= 0) { ++ uasm_i_ehb(p); + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); +- else ++ } else { + UASM_i_LW(p, 1, scratchpad_offset(0), 0); ++ } + } else { + /* Reset default page size */ + if (PM_DEFAULT_MASK >> 16) { +@@ -935,10 +938,12 @@ build_get_pgd_vmalloc64(u32 **p, struct + uasm_i_jr(p, ptr); + + if (mode == refill_scratch) { +- if (scratch_reg >= 0) ++ if (scratch_reg >= 0) { ++ uasm_i_ehb(p); + UASM_i_MFC0(p, 1, c0_kscratch(), scratch_reg); +- else ++ } else { + UASM_i_LW(p, 1, scratchpad_offset(0), 0); ++ } + } else { + uasm_i_nop(p); + } +@@ -1238,6 +1243,7 @@ build_fast_tlb_refill_handler (u32 **p, + UASM_i_MTC0(p, odd, C0_ENTRYLO1); /* load it */ + + if (c0_scratch_reg >= 0) { ++ uasm_i_ehb(p); + UASM_i_MFC0(p, scratch, c0_kscratch(), c0_scratch_reg); + build_tlb_write_entry(p, l, r, tlb_random); + uasm_l_leave(l, *p); +@@ -1592,15 +1598,17 @@ static void build_setup_pgd(void) + uasm_i_dinsm(&p, a0, 0, 29, 64 - 29); + uasm_l_tlbl_goaround1(&l, p); + UASM_i_SLL(&p, a0, a0, 11); +- uasm_i_jr(&p, 31); + UASM_i_MTC0(&p, a0, C0_CONTEXT); ++ uasm_i_jr(&p, 31); ++ uasm_i_ehb(&p); + } else { + /* PGD in c0_KScratch */ +- uasm_i_jr(&p, 31); + if (cpu_has_ldpte) + UASM_i_MTC0(&p, a0, C0_PWBASE); + else + UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); ++ uasm_i_jr(&p, 31); ++ uasm_i_ehb(&p); + } + #else + #ifdef CONFIG_SMP +@@ -1614,13 +1622,16 @@ static void build_setup_pgd(void) + UASM_i_LA_mostly(&p, a2, pgdc); + UASM_i_SW(&p, a0, uasm_rel_lo(pgdc), a2); + #endif /* SMP */ +- uasm_i_jr(&p, 31); + + /* if pgd_reg is allocated, save PGD also to scratch register */ +- if (pgd_reg != -1) ++ if (pgd_reg != -1) { + UASM_i_MTC0(&p, a0, c0_kscratch(), pgd_reg); +- else ++ uasm_i_jr(&p, 31); ++ uasm_i_ehb(&p); ++ } else { ++ uasm_i_jr(&p, 31); + uasm_i_nop(&p); ++ } + #endif + if (p >= tlbmiss_handler_setup_pgd_end) + panic("tlbmiss_handler_setup_pgd space exceeded"); diff --git a/queue-4.9/series b/queue-4.9/series index fcf42810cd0..824a8fa2876 100644 --- a/queue-4.9/series +++ b/queue-4.9/series @@ -97,3 +97,5 @@ tty-rocket-fix-incorrect-forward-declaration-of-rp_i.patch arm64-vdso-define-vdso_-start-end-as-array.patch kvm-lapic-fix-pending-interrupt-in-irr-blocked-by-software-disable-lapic.patch ib-hfi1-close-psm-sdma_progress-sleep-window.patch +mips-add-missing-ehb-in-mtc0-mfc0-sequence.patch +dmaengine-imx-sdma-remove-bd_intr-for-channel0.patch -- 2.47.3