From 9a617f0e109cfba2017d76f807ebb3a00c47bdca Mon Sep 17 00:00:00 2001 From: Vijendar Mukunda Date: Wed, 23 Feb 2022 12:49:33 +0530 Subject: [PATCH] ASoC: amd: vg: update platform clock control sequence Add pre power on widget event. Based on this event update platform clock control sequence. This will fix Codec clock and pll restoration issue during system level resume. Signed-off-by: Vijendar Mukunda Link: https://lore.kernel.org/r/20220223071959.13539-4-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown --- sound/soc/amd/vangogh/acp5x-mach.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/sound/soc/amd/vangogh/acp5x-mach.c b/sound/soc/amd/vangogh/acp5x-mach.c index 14cf325e4b237..e610616d796c0 100644 --- a/sound/soc/amd/vangogh/acp5x-mach.c +++ b/sound/soc/amd/vangogh/acp5x-mach.c @@ -33,6 +33,8 @@ #define DUAL_CHANNEL 2 #define ACP5X_NUVOTON_CODEC_DAI "nau8821-hifi" #define VG_JUPITER 1 +#define ACP5X_NUVOTON_BCLK 3072000 +#define ACP5X_NAU8821_FREQ_OUT 12288000 static unsigned long acp5x_machine_id; static struct snd_soc_jack vg_headset; @@ -274,6 +276,15 @@ static int platform_clock_control(struct snd_soc_dapm_widget *w, dev_err(card->dev, "set sysclk err = %d\n", ret); return -EIO; } + } else { + ret = snd_soc_dai_set_sysclk(codec_dai, NAU8821_CLK_FLL_BLK, 0, + SND_SOC_CLOCK_IN); + if (ret < 0) + dev_err(codec_dai->dev, "can't set BLK clock %d\n", ret); + ret = snd_soc_dai_set_pll(codec_dai, 0, 0, ACP5X_NUVOTON_BCLK, + ACP5X_NAU8821_FREQ_OUT); + if (ret < 0) + dev_err(codec_dai->dev, "can't set FLL: %d\n", ret); } return ret; } @@ -289,7 +300,7 @@ static const struct snd_soc_dapm_widget acp5x_8821_widgets[] = { SND_SOC_DAPM_MIC("Headset Mic", NULL), SND_SOC_DAPM_MIC("Int Mic", NULL), SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0, - platform_clock_control, SND_SOC_DAPM_POST_PMD), + platform_clock_control, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), }; static const struct snd_soc_dapm_route acp5x_8821_audio_route[] = { -- 2.39.5