From 9cd6992bb46f6d36763579c407f1c68ba86fca1d Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 24 May 2021 12:49:13 +0200 Subject: [PATCH] 5.4-stable patches added patches: dm-snapshot-fix-a-crash-when-an-origin-has-no-snapshots.patch dm-snapshot-fix-crash-with-transient-storage-and-zero-chunk-size.patch drm-amdgpu-disable-3dcgcg-on-picasso-raven1-to-avoid-compute-hang.patch drm-amdgpu-update-gc-golden-setting-for-navi12.patch drm-amdgpu-update-sdma-golden-setting-for-navi12.patch mmc-sdhci-pci-gli-increase-1.8v-regulator-wait.patch xen-pciback-reconfigure-also-from-backend-watch-handler.patch --- ...rash-when-an-origin-has-no-snapshots.patch | 43 ++++++++++ ...ransient-storage-and-zero-chunk-size.patch | 41 +++++++++ ...picasso-raven1-to-avoid-compute-hang.patch | 68 +++++++++++++++ ...-update-gc-golden-setting-for-navi12.patch | 49 +++++++++++ ...pdate-sdma-golden-setting-for-navi12.patch | 33 +++++++ ...pci-gli-increase-1.8v-regulator-wait.patch | 53 ++++++++++++ queue-5.4/series | 7 ++ ...gure-also-from-backend-watch-handler.patch | 85 +++++++++++++++++++ 8 files changed, 379 insertions(+) create mode 100644 queue-5.4/dm-snapshot-fix-a-crash-when-an-origin-has-no-snapshots.patch create mode 100644 queue-5.4/dm-snapshot-fix-crash-with-transient-storage-and-zero-chunk-size.patch create mode 100644 queue-5.4/drm-amdgpu-disable-3dcgcg-on-picasso-raven1-to-avoid-compute-hang.patch create mode 100644 queue-5.4/drm-amdgpu-update-gc-golden-setting-for-navi12.patch create mode 100644 queue-5.4/drm-amdgpu-update-sdma-golden-setting-for-navi12.patch create mode 100644 queue-5.4/mmc-sdhci-pci-gli-increase-1.8v-regulator-wait.patch create mode 100644 queue-5.4/xen-pciback-reconfigure-also-from-backend-watch-handler.patch diff --git a/queue-5.4/dm-snapshot-fix-a-crash-when-an-origin-has-no-snapshots.patch b/queue-5.4/dm-snapshot-fix-a-crash-when-an-origin-has-no-snapshots.patch new file mode 100644 index 00000000000..94a509615e2 --- /dev/null +++ b/queue-5.4/dm-snapshot-fix-a-crash-when-an-origin-has-no-snapshots.patch @@ -0,0 +1,43 @@ +From 7ee06ddc4038f936b0d4459d37a7d4d844fb03db Mon Sep 17 00:00:00 2001 +From: Mikulas Patocka +Date: Fri, 7 May 2021 11:38:10 -0400 +Subject: dm snapshot: fix a crash when an origin has no snapshots + +From: Mikulas Patocka + +commit 7ee06ddc4038f936b0d4459d37a7d4d844fb03db upstream. + +If an origin target has no snapshots, o->split_boundary is set to 0. +This causes BUG_ON(sectors <= 0) in block/bio.c:bio_split(). + +Fix this by initializing chunk_size, and in turn split_boundary, to +rounddown_pow_of_two(UINT_MAX) -- the largest power of two that fits +into "unsigned" type. + +Reported-by: Michael Tokarev +Tested-by: Michael Tokarev +Cc: stable@vger.kernel.org +Signed-off-by: Mikulas Patocka +Signed-off-by: Mike Snitzer +Signed-off-by: Greg Kroah-Hartman +--- + drivers/md/dm-snap.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/drivers/md/dm-snap.c ++++ b/drivers/md/dm-snap.c +@@ -854,12 +854,11 @@ static int dm_add_exception(void *contex + static uint32_t __minimum_chunk_size(struct origin *o) + { + struct dm_snapshot *snap; +- unsigned chunk_size = 0; ++ unsigned chunk_size = rounddown_pow_of_two(UINT_MAX); + + if (o) + list_for_each_entry(snap, &o->snapshots, list) +- chunk_size = min_not_zero(chunk_size, +- snap->store->chunk_size); ++ chunk_size = min(chunk_size, snap->store->chunk_size); + + return (uint32_t) chunk_size; + } diff --git a/queue-5.4/dm-snapshot-fix-crash-with-transient-storage-and-zero-chunk-size.patch b/queue-5.4/dm-snapshot-fix-crash-with-transient-storage-and-zero-chunk-size.patch new file mode 100644 index 00000000000..f3d6a700546 --- /dev/null +++ b/queue-5.4/dm-snapshot-fix-crash-with-transient-storage-and-zero-chunk-size.patch @@ -0,0 +1,41 @@ +From c699a0db2d62e3bbb7f0bf35c87edbc8d23e3062 Mon Sep 17 00:00:00 2001 +From: Mikulas Patocka +Date: Mon, 10 May 2021 14:49:05 -0400 +Subject: dm snapshot: fix crash with transient storage and zero chunk size + +From: Mikulas Patocka + +commit c699a0db2d62e3bbb7f0bf35c87edbc8d23e3062 upstream. + +The following commands will crash the kernel: + +modprobe brd rd_size=1048576 +dmsetup create o --table "0 `blockdev --getsize /dev/ram0` snapshot-origin /dev/ram0" +dmsetup create s --table "0 `blockdev --getsize /dev/ram0` snapshot /dev/ram0 /dev/ram1 N 0" + +The reason is that when we test for zero chunk size, we jump to the label +bad_read_metadata without setting the "r" variable. The function +snapshot_ctr destroys all the structures and then exits with "r == 0". The +kernel then crashes because it falsely believes that snapshot_ctr +succeeded. + +In order to fix the bug, we set the variable "r" to -EINVAL. + +Signed-off-by: Mikulas Patocka +Cc: stable@vger.kernel.org +Signed-off-by: Mike Snitzer +Signed-off-by: Greg Kroah-Hartman +--- + drivers/md/dm-snap.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/md/dm-snap.c ++++ b/drivers/md/dm-snap.c +@@ -1407,6 +1407,7 @@ static int snapshot_ctr(struct dm_target + + if (!s->store->chunk_size) { + ti->error = "Chunk size not set"; ++ r = -EINVAL; + goto bad_read_metadata; + } + diff --git a/queue-5.4/drm-amdgpu-disable-3dcgcg-on-picasso-raven1-to-avoid-compute-hang.patch b/queue-5.4/drm-amdgpu-disable-3dcgcg-on-picasso-raven1-to-avoid-compute-hang.patch new file mode 100644 index 00000000000..38c9e38fb50 --- /dev/null +++ b/queue-5.4/drm-amdgpu-disable-3dcgcg-on-picasso-raven1-to-avoid-compute-hang.patch @@ -0,0 +1,68 @@ +From dbd1003d1252db5973dddf20b24bb0106ac52aa2 Mon Sep 17 00:00:00 2001 +From: Changfeng +Date: Fri, 14 May 2021 15:28:25 +0800 +Subject: drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hang + +From: Changfeng + +commit dbd1003d1252db5973dddf20b24bb0106ac52aa2 upstream. + +There is problem with 3DCGCG firmware and it will cause compute test +hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid +compute hang. + +Signed-off-by: Changfeng +Reviewed-by: Alex Deucher +Reviewed-by: Huang Rui +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++++--- + drivers/gpu/drm/amd/amdgpu/soc15.c | 2 -- + 2 files changed, 7 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +@@ -4661,7 +4661,7 @@ static void gfx_v9_0_update_3d_clock_gat + amdgpu_gfx_rlc_enter_safe_mode(adev); + + /* Enable 3D CGCG/CGLS */ +- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { ++ if (enable) { + /* write cmd to clear cgcg/cgls ov */ + def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); + /* unset CGCG override */ +@@ -4673,8 +4673,12 @@ static void gfx_v9_0_update_3d_clock_gat + /* enable 3Dcgcg FSM(0x0000363f) */ + def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); + +- data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | +- RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; ++ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) ++ data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | ++ RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; ++ else ++ data = 0x0 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; ++ + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) + data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | + RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; +--- a/drivers/gpu/drm/amd/amdgpu/soc15.c ++++ b/drivers/gpu/drm/amd/amdgpu/soc15.c +@@ -1132,7 +1132,6 @@ static int soc15_common_early_init(void + adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_CP_LS | +- AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | +@@ -1152,7 +1151,6 @@ static int soc15_common_early_init(void + AMD_CG_SUPPORT_GFX_MGLS | + AMD_CG_SUPPORT_GFX_RLC_LS | + AMD_CG_SUPPORT_GFX_CP_LS | +- AMD_CG_SUPPORT_GFX_3D_CGCG | + AMD_CG_SUPPORT_GFX_3D_CGLS | + AMD_CG_SUPPORT_GFX_CGCG | + AMD_CG_SUPPORT_GFX_CGLS | diff --git a/queue-5.4/drm-amdgpu-update-gc-golden-setting-for-navi12.patch b/queue-5.4/drm-amdgpu-update-gc-golden-setting-for-navi12.patch new file mode 100644 index 00000000000..4eff8e68048 --- /dev/null +++ b/queue-5.4/drm-amdgpu-update-gc-golden-setting-for-navi12.patch @@ -0,0 +1,49 @@ +From 99c45ba5799d6b938bd9bd20edfeb6f3e3e039b9 Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Mon, 17 May 2021 16:35:40 +0800 +Subject: drm/amdgpu: update gc golden setting for Navi12 + +From: Guchun Chen + +commit 99c45ba5799d6b938bd9bd20edfeb6f3e3e039b9 upstream. + +Current golden setting is out of date. + +Signed-off-by: Guchun Chen +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -190,9 +190,10 @@ static const struct soc15_reg_golden gol + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), +- SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), +@@ -210,12 +211,13 @@ static const struct soc15_reg_golden gol + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), +- SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) + }; + + static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = diff --git a/queue-5.4/drm-amdgpu-update-sdma-golden-setting-for-navi12.patch b/queue-5.4/drm-amdgpu-update-sdma-golden-setting-for-navi12.patch new file mode 100644 index 00000000000..2022eb215d5 --- /dev/null +++ b/queue-5.4/drm-amdgpu-update-sdma-golden-setting-for-navi12.patch @@ -0,0 +1,33 @@ +From 77194d8642dd4cb7ea8ced77bfaea55610574c38 Mon Sep 17 00:00:00 2001 +From: Guchun Chen +Date: Mon, 17 May 2021 16:38:00 +0800 +Subject: drm/amdgpu: update sdma golden setting for Navi12 + +From: Guchun Chen + +commit 77194d8642dd4cb7ea8ced77bfaea55610574c38 upstream. + +Current golden setting is out of date. + +Signed-off-by: Guchun Chen +Reviewed-by: Kenneth Feng +Signed-off-by: Alex Deucher +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman +--- + drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +@@ -100,6 +100,10 @@ static const struct soc15_reg_golden gol + + static const struct soc15_reg_golden golden_settings_sdma_nv12[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG, 0x001877ff, 0x00000044), ++ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x001877ff, 0x00000044), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000), + }; + diff --git a/queue-5.4/mmc-sdhci-pci-gli-increase-1.8v-regulator-wait.patch b/queue-5.4/mmc-sdhci-pci-gli-increase-1.8v-regulator-wait.patch new file mode 100644 index 00000000000..cd8300e86d4 --- /dev/null +++ b/queue-5.4/mmc-sdhci-pci-gli-increase-1.8v-regulator-wait.patch @@ -0,0 +1,53 @@ +From a1149a6c06ee094a6e62886b0c0e8e66967a728a Mon Sep 17 00:00:00 2001 +From: Daniel Beer +Date: Sat, 24 Apr 2021 20:16:52 +1200 +Subject: mmc: sdhci-pci-gli: increase 1.8V regulator wait + +From: Daniel Beer + +commit a1149a6c06ee094a6e62886b0c0e8e66967a728a upstream. + +Inserting an SD-card on an Intel NUC10i3FNK4 (which contains a GL9755) +results in the message: + + mmc0: 1.8V regulator output did not become stable + +Following this message, some cards work (sometimes), but most cards fail +with EILSEQ. This behaviour is observed on Debian 10 running kernel +4.19.188, but also with 5.8.18 and 5.11.15. + +The driver currently waits 5ms after switching on the 1.8V regulator for +it to become stable. Increasing this to 10ms gets rid of the warning +about stability, but most cards still fail. Increasing it to 20ms gets +some cards working (a 32GB Samsung micro SD works, a 128GB ADATA +doesn't). At 50ms, the ADATA works most of the time, and at 100ms both +cards work reliably. + +Signed-off-by: Daniel Beer +Acked-by: Ben Chuang +Fixes: e51df6ce668a ("mmc: host: sdhci-pci: Add Genesys Logic GL975x support") +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/20210424081652.GA16047@nyquist.nev +Signed-off-by: Ulf Hansson +Signed-off-by: Greg Kroah-Hartman +--- + drivers/mmc/host/sdhci-pci-gli.c | 7 ++++++- + 1 file changed, 6 insertions(+), 1 deletion(-) + +--- a/drivers/mmc/host/sdhci-pci-gli.c ++++ b/drivers/mmc/host/sdhci-pci-gli.c +@@ -318,8 +318,13 @@ static void sdhci_gli_voltage_switch(str + * + * Wait 5ms after set 1.8V signal enable in Host Control 2 register + * to ensure 1.8V signal enable bit is set by GL9750/GL9755. ++ * ++ * ...however, the controller in the NUC10i3FNK4 (a 9755) requires ++ * slightly longer than 5ms before the control register reports that ++ * 1.8V is ready, and far longer still before the card will actually ++ * work reliably. + */ +- usleep_range(5000, 5500); ++ usleep_range(100000, 110000); + } + + static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) diff --git a/queue-5.4/series b/queue-5.4/series index 132a256e8e8..eda3b35a172 100644 --- a/queue-5.4/series +++ b/queue-5.4/series @@ -34,3 +34,10 @@ uio_hv_generic-fix-a-memory-leak-in-error-handling-paths.patch revert-rapidio-fix-a-null-pointer-dereference-when-create_workqueue-fails.patch rapidio-handle-create_workqueue-failure.patch revert-serial-mvebu-uart-fix-to-avoid-a-potential-null-pointer-dereference.patch +drm-amdgpu-disable-3dcgcg-on-picasso-raven1-to-avoid-compute-hang.patch +drm-amdgpu-update-gc-golden-setting-for-navi12.patch +drm-amdgpu-update-sdma-golden-setting-for-navi12.patch +mmc-sdhci-pci-gli-increase-1.8v-regulator-wait.patch +xen-pciback-reconfigure-also-from-backend-watch-handler.patch +dm-snapshot-fix-a-crash-when-an-origin-has-no-snapshots.patch +dm-snapshot-fix-crash-with-transient-storage-and-zero-chunk-size.patch diff --git a/queue-5.4/xen-pciback-reconfigure-also-from-backend-watch-handler.patch b/queue-5.4/xen-pciback-reconfigure-also-from-backend-watch-handler.patch new file mode 100644 index 00000000000..c2967a57b9d --- /dev/null +++ b/queue-5.4/xen-pciback-reconfigure-also-from-backend-watch-handler.patch @@ -0,0 +1,85 @@ +From c81d3d24602540f65256f98831d0a25599ea6b87 Mon Sep 17 00:00:00 2001 +From: Jan Beulich +Date: Tue, 18 May 2021 18:14:07 +0200 +Subject: xen-pciback: reconfigure also from backend watch handler + +From: Jan Beulich + +commit c81d3d24602540f65256f98831d0a25599ea6b87 upstream. + +When multiple PCI devices get assigned to a guest right at boot, libxl +incrementally populates the backend tree. The writes for the first of +the devices trigger the backend watch. In turn xen_pcibk_setup_backend() +will set the XenBus state to Initialised, at which point no further +reconfigures would happen unless a device got hotplugged. Arrange for +reconfigure to also get triggered from the backend watch handler. + +Signed-off-by: Jan Beulich +Cc: stable@vger.kernel.org +Reviewed-by: Boris Ostrovsky +Link: https://lore.kernel.org/r/2337cbd6-94b9-4187-9862-c03ea12e0c61@suse.com +Signed-off-by: Juergen Gross +Signed-off-by: Greg Kroah-Hartman +--- + drivers/xen/xen-pciback/xenbus.c | 22 +++++++++++++++++----- + 1 file changed, 17 insertions(+), 5 deletions(-) + +--- a/drivers/xen/xen-pciback/xenbus.c ++++ b/drivers/xen/xen-pciback/xenbus.c +@@ -358,7 +358,8 @@ out: + return err; + } + +-static int xen_pcibk_reconfigure(struct xen_pcibk_device *pdev) ++static int xen_pcibk_reconfigure(struct xen_pcibk_device *pdev, ++ enum xenbus_state state) + { + int err = 0; + int num_devs; +@@ -372,9 +373,7 @@ static int xen_pcibk_reconfigure(struct + dev_dbg(&pdev->xdev->dev, "Reconfiguring device ...\n"); + + mutex_lock(&pdev->dev_lock); +- /* Make sure we only reconfigure once */ +- if (xenbus_read_driver_state(pdev->xdev->nodename) != +- XenbusStateReconfiguring) ++ if (xenbus_read_driver_state(pdev->xdev->nodename) != state) + goto out; + + err = xenbus_scanf(XBT_NIL, pdev->xdev->nodename, "num_devs", "%d", +@@ -499,6 +498,10 @@ static int xen_pcibk_reconfigure(struct + } + } + ++ if (state != XenbusStateReconfiguring) ++ /* Make sure we only reconfigure once. */ ++ goto out; ++ + err = xenbus_switch_state(pdev->xdev, XenbusStateReconfigured); + if (err) { + xenbus_dev_fatal(pdev->xdev, err, +@@ -524,7 +527,7 @@ static void xen_pcibk_frontend_changed(s + break; + + case XenbusStateReconfiguring: +- xen_pcibk_reconfigure(pdev); ++ xen_pcibk_reconfigure(pdev, XenbusStateReconfiguring); + break; + + case XenbusStateConnected: +@@ -663,6 +666,15 @@ static void xen_pcibk_be_watch(struct xe + xen_pcibk_setup_backend(pdev); + break; + ++ case XenbusStateInitialised: ++ /* ++ * We typically move to Initialised when the first device was ++ * added. Hence subsequent devices getting added may need ++ * reconfiguring. ++ */ ++ xen_pcibk_reconfigure(pdev, XenbusStateInitialised); ++ break; ++ + default: + break; + } -- 2.47.3