From 9ed225f1baf7533cd701b4d8518ffb5c531ccaaa Mon Sep 17 00:00:00 2001 From: Rob Bradford Date: Mon, 30 Sep 2024 17:52:57 +0100 Subject: [PATCH] target/riscv: Set vtype.vill on CPU reset The RISC-V unprivileged specification "31.3.11. State of Vector Extension at Reset" has a note that recommends vtype.vill be set on reset as part of ensuring that the vector extension have a consistent state at reset. This change now makes QEMU consistent with Spike which sets vtype.vill on reset. Signed-off-by: Rob Bradford Reviewed-by: Daniel Henrique Barboza Message-ID: <20240930165258.72258-1-rbradford@rivosinc.com> Signed-off-by: Alistair Francis (cherry picked from commit f8c1f36a2e3dab4935e7c5690e578ac71765766b) Signed-off-by: Michael Tokarev --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 77cb59b8a17..eb0e8560560 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -910,6 +910,7 @@ static void riscv_cpu_reset_hold(Object *obj) cs->exception_index = RISCV_EXCP_NONE; env->load_res = -1; set_default_nan_mode(1, &env->fp_status); + env->vill = true; #ifndef CONFIG_USER_ONLY if (cpu->cfg.debug) { -- 2.39.5