From a1cec1ec0aecd87c9e4cdafaf21b3581bbfa0c1c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Mon, 16 May 2016 11:25:49 -0700 Subject: [PATCH] 3.14-stable patches added patches: drm-i915-bail-out-of-pipe-config-compute-loop-on-lpt.patch drm-radeon-fix-pll-sharing-on-dce6.1-v2.patch --- ...t-of-pipe-config-compute-loop-on-lpt.patch | 48 +++++++++++++ ...-radeon-fix-pll-sharing-on-dce6.1-v2.patch | 71 +++++++++++++++++++ queue-3.14/series | 2 + 3 files changed, 121 insertions(+) create mode 100644 queue-3.14/drm-i915-bail-out-of-pipe-config-compute-loop-on-lpt.patch create mode 100644 queue-3.14/drm-radeon-fix-pll-sharing-on-dce6.1-v2.patch diff --git a/queue-3.14/drm-i915-bail-out-of-pipe-config-compute-loop-on-lpt.patch b/queue-3.14/drm-i915-bail-out-of-pipe-config-compute-loop-on-lpt.patch new file mode 100644 index 00000000000..0e33fa195b4 --- /dev/null +++ b/queue-3.14/drm-i915-bail-out-of-pipe-config-compute-loop-on-lpt.patch @@ -0,0 +1,48 @@ +From 2700818ac9f935d8590715eecd7e8cadbca552b6 Mon Sep 17 00:00:00 2001 +From: Daniel Vetter +Date: Tue, 3 May 2016 10:33:01 +0200 +Subject: drm/i915: Bail out of pipe config compute loop on LPT + +From: Daniel Vetter + +commit 2700818ac9f935d8590715eecd7e8cadbca552b6 upstream. + +LPT is pch, so might run into the fdi bandwidth constraint (especially +since it has only 2 lanes). But right now we just force pipe_bpp back +to 24, resulting in a nice loop (which we bail out with a loud +WARN_ON). Fix this. + +Cc: Chris Wilson +Cc: Maarten Lankhorst +References: https://bugs.freedesktop.org/show_bug.cgi?id=93477 +Signed-off-by: Daniel Vetter +Tested-by: Chris Wilson +Signed-off-by: Maarten Lankhorst +Signed-off-by: Daniel Vetter +Link: http://patchwork.freedesktop.org/patch/msgid/1462264381-7573-1-git-send-email-daniel.vetter@ffwll.ch +(cherry picked from commit f58a1acc7e4a1f37d26124ce4c875c647fbcc61f) +Signed-off-by: Jani Nikula +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/i915/intel_crt.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/gpu/drm/i915/intel_crt.c ++++ b/drivers/gpu/drm/i915/intel_crt.c +@@ -259,8 +259,14 @@ static bool intel_crt_compute_config(str + pipe_config->has_pch_encoder = true; + + /* LPT FDI RX only supports 8bpc. */ +- if (HAS_PCH_LPT(dev)) ++ if (HAS_PCH_LPT(dev)) { ++ if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { ++ DRM_DEBUG_KMS("LPT only supports 24bpp\n"); ++ return false; ++ } ++ + pipe_config->pipe_bpp = 24; ++ } + + return true; + } diff --git a/queue-3.14/drm-radeon-fix-pll-sharing-on-dce6.1-v2.patch b/queue-3.14/drm-radeon-fix-pll-sharing-on-dce6.1-v2.patch new file mode 100644 index 00000000000..d8d5b48f761 --- /dev/null +++ b/queue-3.14/drm-radeon-fix-pll-sharing-on-dce6.1-v2.patch @@ -0,0 +1,71 @@ +From e3c00d87845ab375f90fa6e10a5e72a3a5778cd3 Mon Sep 17 00:00:00 2001 +From: Lucas Stach +Date: Thu, 5 May 2016 10:16:44 -0400 +Subject: drm/radeon: fix PLL sharing on DCE6.1 (v2) + +From: Lucas Stach + +commit e3c00d87845ab375f90fa6e10a5e72a3a5778cd3 upstream. + +On DCE6.1 PPLL2 is exclusively available to UNIPHYA, so it should not +be taken into consideration when looking for an already enabled PLL +to be shared with other outputs. + +This fixes the broken VGA port (TRAVIS DP->VGA bridge) on my Richland +based laptop, where the internal display is connected to UNIPHYA through +a TRAVIS DP->LVDS bridge. + +Bug: +https://bugs.freedesktop.org/show_bug.cgi?id=78987 + +v2: agd: add check in radeon_get_shared_nondp_ppll as well, drop + extra parameter. + +Signed-off-by: Lucas Stach +Signed-off-by: Alex Deucher +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/gpu/drm/radeon/atombios_crtc.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/gpu/drm/radeon/atombios_crtc.c ++++ b/drivers/gpu/drm/radeon/atombios_crtc.c +@@ -1600,6 +1600,7 @@ static u32 radeon_get_pll_use_mask(struc + static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) + { + struct drm_device *dev = crtc->dev; ++ struct radeon_device *rdev = dev->dev_private; + struct drm_crtc *test_crtc; + struct radeon_crtc *test_radeon_crtc; + +@@ -1609,6 +1610,10 @@ static int radeon_get_shared_dp_ppll(str + test_radeon_crtc = to_radeon_crtc(test_crtc); + if (test_radeon_crtc->encoder && + ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { ++ /* PPLL2 is exclusive to UNIPHYA on DCE61 */ ++ if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && ++ test_radeon_crtc->pll_id == ATOM_PPLL2) ++ continue; + /* for DP use the same PLL for all */ + if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) + return test_radeon_crtc->pll_id; +@@ -1630,6 +1635,7 @@ static int radeon_get_shared_nondp_ppll( + { + struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); + struct drm_device *dev = crtc->dev; ++ struct radeon_device *rdev = dev->dev_private; + struct drm_crtc *test_crtc; + struct radeon_crtc *test_radeon_crtc; + u32 adjusted_clock, test_adjusted_clock; +@@ -1645,6 +1651,10 @@ static int radeon_get_shared_nondp_ppll( + test_radeon_crtc = to_radeon_crtc(test_crtc); + if (test_radeon_crtc->encoder && + !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { ++ /* PPLL2 is exclusive to UNIPHYA on DCE61 */ ++ if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && ++ test_radeon_crtc->pll_id == ATOM_PPLL2) ++ continue; + /* check if we are already driving this connector with another crtc */ + if (test_radeon_crtc->connector == radeon_crtc->connector) { + /* if we are, return that pll */ diff --git a/queue-3.14/series b/queue-3.14/series index 90de2d0a770..58885017bd4 100644 --- a/queue-3.14/series +++ b/queue-3.14/series @@ -2,3 +2,5 @@ crypto-hash-fix-page-length-clamping-in-hash-walk.patch get_rock_ridge_filename-handle-malformed-nm-entries.patch input-max8997-haptic-fix-null-pointer-dereference.patch asmlinkage-pnp-make-variables-used-from-assembler-code-visible.patch +drm-radeon-fix-pll-sharing-on-dce6.1-v2.patch +drm-i915-bail-out-of-pipe-config-compute-loop-on-lpt.patch -- 2.47.3