From a3d6596ecf1cac1f81f121cb23a815895ae70645 Mon Sep 17 00:00:00 2001 From: Jiawei Date: Sun, 11 May 2025 21:38:19 +0800 Subject: [PATCH] RISC-V: Add support for RISC-V Profiles 23. This patch adds support for RISC-V RVA23 and RVB23 Profiles[1]. [1] https://github.com/riscv/riscv-profiles/releases/tag/rva23-rvb23-ratified bfd/ChangeLog: * elfxx-riscv.c: New profiles. gas/ChangeLog: * testsuite/gas/riscv/attribute-19.d: New test. * testsuite/gas/riscv/attribute-20.d: New test. --- bfd/elfxx-riscv.c | 16 ++++++++++++++++ gas/testsuite/gas/riscv/attribute-19.d | 6 ++++++ gas/testsuite/gas/riscv/attribute-20.d | 6 ++++++ 3 files changed, 28 insertions(+) create mode 100644 gas/testsuite/gas/riscv/attribute-19.d create mode 100644 gas/testsuite/gas/riscv/attribute-20.d diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index f4d392413e9..085a6ebffa4 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1338,6 +1338,22 @@ static struct riscv_profiles riscv_profiles_table[] = "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" "_zicboz_zfhmin_zkt"}, + /* RVA23 contains all mandatory base ISA for RVA22U64 and the new extension + 'v,zihintntl,zvfhmin,zvbb,zvkt,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"rva23u64", "rv64imafdcv_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zvfhmin_zvbb_zvkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + + /* RVB23 contains all mandatory base ISA for RVA22U64 and the new extension + 'zihintntl,zicond,zimop,zcmop,zfa,zawrs' as mandatory + extensions. */ + {"rvb23u64", "rv64imafdc_zicsr_zicntr_zihpm_ziccif_ziccrse_ziccamoa" + "_zicclsm_zic64b_za64rs_zihintpause_zba_zbb_zbs_zicbom_zicbop" + "_zicboz_zfhmin_zkt_zihintntl_zicond_zimop_zcmop_zcb" + "_zfa_zawrs"}, + /* Currently we do not define S/M mode Profiles. */ /* Terminate the list. */ diff --git a/gas/testsuite/gas/riscv/attribute-19.d b/gas/testsuite/gas/riscv/attribute-19.d new file mode 100644 index 00000000000..1cd15d5b109 --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-19.d @@ -0,0 +1,6 @@ +#as: -march=rva23u64 -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" diff --git a/gas/testsuite/gas/riscv/attribute-20.d b/gas/testsuite/gas/riscv/attribute-20.d new file mode 100644 index 00000000000..e8fb7678a1a --- /dev/null +++ b/gas/testsuite/gas/riscv/attribute-20.d @@ -0,0 +1,6 @@ +#as: -march=rvb23u64 -misa-spec=20191213 +#readelf: -A +#source: empty.s +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" -- 2.39.5