From a40a04601fb16b67bd6c61bb0d79e2c8f9736c9a Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 23 Feb 2024 11:59:09 +0100 Subject: [PATCH] x86: also permit YMM/ZMM use in CFI directives Next to code using %ymm or %zmm it is more natural to have .cfi_* directives also reference those, not the corresponding %xmm. Accept their names as kind of aliases, i.e. resolving to the same numbers. While extending the respective 64-bit testcase, also add %bnd there (should have happened right with 633789901c83 ["x86-64: Dwarf2 register numbers for %bnd"], sorry), requiring binutils/dwarf.c to be adjusted accordingly as well. --- binutils/dwarf.c | 3 +- gas/testsuite/gas/cfi/cfi-i386.d | 55 ++++-- gas/testsuite/gas/cfi/cfi-i386.s | 18 ++ gas/testsuite/gas/cfi/cfi-x86_64.d | 155 +++++++++++++++-- gas/testsuite/gas/cfi/cfi-x86_64.s | 71 ++++++++ gas/testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d | 157 ++++++++++++++++-- opcodes/i386-reg.tbl | 129 +++++++------- opcodes/i386-tbl.h | 128 +++++++------- 8 files changed, 553 insertions(+), 163 deletions(-) diff --git a/binutils/dwarf.c b/binutils/dwarf.c index 1947ab180ee..1491e8db03a 100644 --- a/binutils/dwarf.c +++ b/binutils/dwarf.c @@ -8654,7 +8654,8 @@ static const char *const dwarf_regnames_x86_64[] = NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 99 - 106 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 107 - 114 */ NULL, NULL, NULL, /* 115 - 117 */ - "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" + "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", + "bnd0", "bnd1", "bnd2", "bnd3", }; static void diff --git a/gas/testsuite/gas/cfi/cfi-i386.d b/gas/testsuite/gas/cfi/cfi-i386.d index bf085099337..79d08f4a86f 100644 --- a/gas/testsuite/gas/cfi/cfi-i386.d +++ b/gas/testsuite/gas/cfi/cfi-i386.d @@ -58,7 +58,7 @@ Contents of the .eh_frame section: DW_CFA_undefined: r8 \(eip\) DW_CFA_nop -0+00a0 0+00ac 0+0018 FDE cie=0+008c pc=0+0044..0+0079 +0+00a0 0+[0-9a-f]+ 0+0018 FDE cie=0+008c pc=0+0044\..* DW_CFA_advance_loc: 1 to 0+0045 DW_CFA_undefined: r0 \(eax\) DW_CFA_advance_loc: 1 to 0+0046 @@ -147,23 +147,52 @@ Contents of the .eh_frame section: DW_CFA_undefined: r35 \(mm6\) DW_CFA_advance_loc: 1 to 0+0070 DW_CFA_undefined: r36 \(mm7\) - DW_CFA_advance_loc: 1 to 0+0071 + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r21 \([xy]mm0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r22 \([xy]mm1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r23 \([xy]mm2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r24 \([xy]mm3\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r25 \([xy]mm4\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r26 \([xy]mm5\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r27 \([xy]mm6\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r28 \([xy]mm7\) + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r93 \(k0\) - DW_CFA_advance_loc: 1 to 0+0072 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r94 \(k1\) - DW_CFA_advance_loc: 1 to 0+0073 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r95 \(k2\) - DW_CFA_advance_loc: 1 to 0+0074 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r96 \(k3\) - DW_CFA_advance_loc: 1 to 0+0075 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r97 \(k4\) - DW_CFA_advance_loc: 1 to 0+0076 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r98 \(k5\) - DW_CFA_advance_loc: 1 to 0+0077 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r99 \(k6\) - DW_CFA_advance_loc: 1 to 0+0078 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r100 \(k7\) - DW_CFA_nop - DW_CFA_nop - DW_CFA_nop - + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r21 \([xyz]mm0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r22 \([xyz]mm1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r23 \([xyz]mm2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r24 \([xyz]mm3\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r25 \([xyz]mm4\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r26 \([xyz]mm5\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r27 \([xyz]mm6\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r28 \([xyz]mm7\) +#pass diff --git a/gas/testsuite/gas/cfi/cfi-i386.s b/gas/testsuite/gas/cfi/cfi-i386.s index 0816a0c524b..d4ab3a6eeed 100644 --- a/gas/testsuite/gas/cfi/cfi-i386.s +++ b/gas/testsuite/gas/cfi/cfi-i386.s @@ -157,6 +157,15 @@ func_all_registers: .cfi_undefined mm6 ; nop .cfi_undefined mm7 ; nop + .cfi_undefined ymm0 ; nop + .cfi_undefined ymm1 ; nop + .cfi_undefined ymm2 ; nop + .cfi_undefined ymm3 ; nop + .cfi_undefined ymm4 ; nop + .cfi_undefined ymm5 ; nop + .cfi_undefined ymm6 ; nop + .cfi_undefined ymm7 ; nop + .cfi_undefined k0 ; nop .cfi_undefined k1 ; nop .cfi_undefined k2 ; nop @@ -166,4 +175,13 @@ func_all_registers: .cfi_undefined k6 ; nop .cfi_undefined k7 ; nop + .cfi_undefined zmm0 ; nop + .cfi_undefined zmm1 ; nop + .cfi_undefined zmm2 ; nop + .cfi_undefined zmm3 ; nop + .cfi_undefined zmm4 ; nop + .cfi_undefined zmm5 ; nop + .cfi_undefined zmm6 ; nop + .cfi_undefined zmm7 ; nop + .cfi_endproc diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.d b/gas/testsuite/gas/cfi/cfi-x86_64.d index ad25c35fc36..6dd58f50cf5 100644 --- a/gas/testsuite/gas/cfi/cfi-x86_64.d +++ b/gas/testsuite/gas/cfi/cfi-x86_64.d @@ -96,7 +96,7 @@ Contents of the .eh_frame section: DW_CFA_undefined: r16 \(rip\) DW_CFA_nop -0+00e8 0+011[04] 0+0018 FDE cie=0+00d4 pc=0+0058..0+00af +0+00e8 0+[0-9a-f]+ 0+0018 FDE cie=0+00d4 pc=0+0058\..* DW_CFA_advance_loc: 1 to 0+0059 DW_CFA_undefined: r0 \(rax\) DW_CFA_advance_loc: 1 to 0+005a @@ -253,21 +253,156 @@ Contents of the .eh_frame section: DW_CFA_undefined: r81 \(xmm30\) DW_CFA_advance_loc: 1 to 0+00a6 DW_CFA_undefined: r82 \(xmm31\) - DW_CFA_advance_loc: 1 to 0+00a7 + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r17 \([xy]mm0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r18 \([xy]mm1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r19 \([xy]mm2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r20 \([xy]mm3\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r21 \([xy]mm4\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r22 \([xy]mm5\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r23 \([xy]mm6\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r24 \([xy]mm7\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r25 \([xy]mm8\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r26 \([xy]mm9\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r27 \([xy]mm10\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r28 \([xy]mm11\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r29 \([xy]mm12\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r30 \([xy]mm13\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r31 \([xy]mm14\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r32 \([xy]mm15\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r67 \([xy]mm16\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r68 \([xy]mm17\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r69 \([xy]mm18\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r70 \([xy]mm19\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r71 \([xy]mm20\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r72 \([xy]mm21\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r73 \([xy]mm22\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r74 \([xy]mm23\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r75 \([xy]mm24\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r76 \([xy]mm25\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r77 \([xy]mm26\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r78 \([xy]mm27\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r79 \([xy]mm28\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r80 \([xy]mm29\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r81 \([xy]mm30\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r82 \([xy]mm31\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r126 \(bnd0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r127 \(bnd1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r128 \(bnd2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r129 \(bnd3\) + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r118 \(k0\) - DW_CFA_advance_loc: 1 to 0+00a8 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r119 \(k1\) - DW_CFA_advance_loc: 1 to 0+00a9 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r120 \(k2\) - DW_CFA_advance_loc: 1 to 0+00aa + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r121 \(k3\) - DW_CFA_advance_loc: 1 to 0+00ab + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r122 \(k4\) - DW_CFA_advance_loc: 1 to 0+00ac + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r123 \(k5\) - DW_CFA_advance_loc: 1 to 0+00ad + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r124 \(k6\) - DW_CFA_advance_loc: 1 to 0+00ae + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r125 \(k7\) - DW_CFA_nop + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r17 \([xyz]mm0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r18 \([xyz]mm1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r19 \([xyz]mm2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r20 \([xyz]mm3\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r21 \([xyz]mm4\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r22 \([xyz]mm5\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r23 \([xyz]mm6\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r24 \([xyz]mm7\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r25 \([xyz]mm8\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r26 \([xyz]mm9\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r27 \([xyz]mm10\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r28 \([xyz]mm11\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r29 \([xyz]mm12\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r30 \([xyz]mm13\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r31 \([xyz]mm14\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r32 \([xyz]mm15\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r67 \([xyz]mm16\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r68 \([xyz]mm17\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r69 \([xyz]mm18\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r70 \([xyz]mm19\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r71 \([xyz]mm20\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r72 \([xyz]mm21\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r73 \([xyz]mm22\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r74 \([xyz]mm23\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r75 \([xyz]mm24\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r76 \([xyz]mm25\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r77 \([xyz]mm26\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r78 \([xyz]mm27\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r79 \([xyz]mm28\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r80 \([xyz]mm29\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r81 \([xyz]mm30\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r82 \([xyz]mm31\) #pass diff --git a/gas/testsuite/gas/cfi/cfi-x86_64.s b/gas/testsuite/gas/cfi/cfi-x86_64.s index bc69fff0d5f..1ac7d1cfa2c 100644 --- a/gas/testsuite/gas/cfi/cfi-x86_64.s +++ b/gas/testsuite/gas/cfi/cfi-x86_64.s @@ -221,6 +221,44 @@ func_all_registers: .cfi_undefined xmm30 ; nop .cfi_undefined xmm31 ; nop + .cfi_undefined ymm0 ; nop + .cfi_undefined ymm1 ; nop + .cfi_undefined ymm2 ; nop + .cfi_undefined ymm3 ; nop + .cfi_undefined ymm4 ; nop + .cfi_undefined ymm5 ; nop + .cfi_undefined ymm6 ; nop + .cfi_undefined ymm7 ; nop + .cfi_undefined ymm8 ; nop + .cfi_undefined ymm9 ; nop + .cfi_undefined ymm10 ; nop + .cfi_undefined ymm11 ; nop + .cfi_undefined ymm12 ; nop + .cfi_undefined ymm13 ; nop + .cfi_undefined ymm14 ; nop + .cfi_undefined ymm15 ; nop + .cfi_undefined ymm16 ; nop + .cfi_undefined ymm17 ; nop + .cfi_undefined ymm18 ; nop + .cfi_undefined ymm19 ; nop + .cfi_undefined ymm20 ; nop + .cfi_undefined ymm21 ; nop + .cfi_undefined ymm22 ; nop + .cfi_undefined ymm23 ; nop + .cfi_undefined ymm24 ; nop + .cfi_undefined ymm25 ; nop + .cfi_undefined ymm26 ; nop + .cfi_undefined ymm27 ; nop + .cfi_undefined ymm28 ; nop + .cfi_undefined ymm29 ; nop + .cfi_undefined ymm30 ; nop + .cfi_undefined ymm31 ; nop + + .cfi_undefined bnd0 ; nop + .cfi_undefined bnd1 ; nop + .cfi_undefined bnd2 ; nop + .cfi_undefined bnd3 ; nop + .cfi_undefined k0 ; nop .cfi_undefined k1 ; nop .cfi_undefined k2 ; nop @@ -230,4 +268,37 @@ func_all_registers: .cfi_undefined k6 ; nop .cfi_undefined k7 ; nop + .cfi_undefined zmm0 ; nop + .cfi_undefined zmm1 ; nop + .cfi_undefined zmm2 ; nop + .cfi_undefined zmm3 ; nop + .cfi_undefined zmm4 ; nop + .cfi_undefined zmm5 ; nop + .cfi_undefined zmm6 ; nop + .cfi_undefined zmm7 ; nop + .cfi_undefined zmm8 ; nop + .cfi_undefined zmm9 ; nop + .cfi_undefined zmm10 ; nop + .cfi_undefined zmm11 ; nop + .cfi_undefined zmm12 ; nop + .cfi_undefined zmm13 ; nop + .cfi_undefined zmm14 ; nop + .cfi_undefined zmm15 ; nop + .cfi_undefined zmm16 ; nop + .cfi_undefined zmm17 ; nop + .cfi_undefined zmm18 ; nop + .cfi_undefined zmm19 ; nop + .cfi_undefined zmm20 ; nop + .cfi_undefined zmm21 ; nop + .cfi_undefined zmm22 ; nop + .cfi_undefined zmm23 ; nop + .cfi_undefined zmm24 ; nop + .cfi_undefined zmm25 ; nop + .cfi_undefined zmm26 ; nop + .cfi_undefined zmm27 ; nop + .cfi_undefined zmm28 ; nop + .cfi_undefined zmm29 ; nop + .cfi_undefined zmm30 ; nop + .cfi_undefined zmm31 ; nop + .cfi_endproc diff --git a/gas/testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d b/gas/testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d index c357286b902..d35ceffd116 100644 --- a/gas/testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d +++ b/gas/testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d @@ -96,7 +96,7 @@ Contents of the .eh_frame section: DW_CFA_undefined: r16 \(rip\) DW_CFA_nop -000000e8 0000011[04] 00000018 FDE cie=000000d4 pc=00000058..000000af +000000e8 0000[0-9a-f]+ 00000018 FDE cie=000000d4 pc=00000058\..* DW_CFA_advance_loc: 1 to 00000059 DW_CFA_undefined: r0 \(rax\) DW_CFA_advance_loc: 1 to 0000005a @@ -253,21 +253,156 @@ Contents of the .eh_frame section: DW_CFA_undefined: r81 \(xmm30\) DW_CFA_advance_loc: 1 to 000000a6 DW_CFA_undefined: r82 \(xmm31\) - DW_CFA_advance_loc: 1 to 000000a7 + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r17 \([xy]mm0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r18 \([xy]mm1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r19 \([xy]mm2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r20 \([xy]mm3\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r21 \([xy]mm4\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r22 \([xy]mm5\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r23 \([xy]mm6\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r24 \([xy]mm7\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r25 \([xy]mm8\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r26 \([xy]mm9\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r27 \([xy]mm10\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r28 \([xy]mm11\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r29 \([xy]mm12\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r30 \([xy]mm13\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r31 \([xy]mm14\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r32 \([xy]mm15\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r67 \([xy]mm16\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r68 \([xy]mm17\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r69 \([xy]mm18\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r70 \([xy]mm19\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r71 \([xy]mm20\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r72 \([xy]mm21\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r73 \([xy]mm22\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r74 \([xy]mm23\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r75 \([xy]mm24\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r76 \([xy]mm25\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r77 \([xy]mm26\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r78 \([xy]mm27\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r79 \([xy]mm28\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r80 \([xy]mm29\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r81 \([xy]mm30\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r82 \([xy]mm31\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r126 \(bnd0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r127 \(bnd1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r128 \(bnd2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r129 \(bnd3\) + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r118 \(k0\) - DW_CFA_advance_loc: 1 to 000000a8 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r119 \(k1\) - DW_CFA_advance_loc: 1 to 000000a9 + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r120 \(k2\) - DW_CFA_advance_loc: 1 to 000000aa + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r121 \(k3\) - DW_CFA_advance_loc: 1 to 000000ab + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r122 \(k4\) - DW_CFA_advance_loc: 1 to 000000ac + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r123 \(k5\) - DW_CFA_advance_loc: 1 to 000000ad + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r124 \(k6\) - DW_CFA_advance_loc: 1 to 000000ae + DW_CFA_advance_loc: 1 to .* DW_CFA_undefined: r125 \(k7\) - DW_CFA_nop - + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r17 \([xyz]mm0\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r18 \([xyz]mm1\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r19 \([xyz]mm2\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r20 \([xyz]mm3\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r21 \([xyz]mm4\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r22 \([xyz]mm5\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r23 \([xyz]mm6\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r24 \([xyz]mm7\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r25 \([xyz]mm8\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r26 \([xyz]mm9\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r27 \([xyz]mm10\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r28 \([xyz]mm11\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r29 \([xyz]mm12\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r30 \([xyz]mm13\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r31 \([xyz]mm14\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r32 \([xyz]mm15\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r67 \([xyz]mm16\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r68 \([xyz]mm17\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r69 \([xyz]mm18\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r70 \([xyz]mm19\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r71 \([xyz]mm20\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r72 \([xyz]mm21\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r73 \([xyz]mm22\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r74 \([xyz]mm23\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r75 \([xyz]mm24\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r76 \([xyz]mm25\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r77 \([xyz]mm26\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r78 \([xyz]mm27\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r79 \([xyz]mm28\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r80 \([xyz]mm29\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r81 \([xyz]mm30\) + DW_CFA_advance_loc: 1 to .* + DW_CFA_undefined: r82 \([xyz]mm31\) +#pass diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index 87d2665243d..d441f364a04 100644 --- a/opcodes/i386-reg.tbl +++ b/opcodes/i386-reg.tbl @@ -278,71 +278,72 @@ xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80 xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81 xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82 // AVX registers. -ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval -ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval -ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval -ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval -ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval -ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval -ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval -ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval -ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval -ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval -ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval -ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval -ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval -ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval -ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval -ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval -ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval -ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval -ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval -ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval -ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval -ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval -ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval -ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval -ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval -ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval -ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval -ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval -ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval -ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval -ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval -ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval +ymm0, Class=RegSIMD|Ymmword, 0, 0, 21, 17 +ymm1, Class=RegSIMD|Ymmword, 0, 1, 22, 18 +ymm2, Class=RegSIMD|Ymmword, 0, 2, 23, 19 +ymm3, Class=RegSIMD|Ymmword, 0, 3, 24, 20 +ymm4, Class=RegSIMD|Ymmword, 0, 4, 25, 21 +ymm5, Class=RegSIMD|Ymmword, 0, 5, 26, 22 +ymm6, Class=RegSIMD|Ymmword, 0, 6, 27, 23 +ymm7, Class=RegSIMD|Ymmword, 0, 7, 28, 24 +ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, 25 +ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, 26 +ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, 27 +ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, 28 +ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, 29 +ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, 30 +ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, 31 +ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, 32 +// AVX512 / AVX10 registers. +ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, 67 +ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, 68 +ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, 69 +ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, 70 +ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, 71 +ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, 72 +ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, 73 +ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, 74 +ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, 75 +ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, 76 +ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, 77 +ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, 78 +ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, 79 +ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, 80 +ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, 81 +ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, 82 // AVX512 registers. -zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval -zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval -zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval -zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval -zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval -zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval -zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval -zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval -zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval -zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval -zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval -zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval -zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval -zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval -zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval -zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval -zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval -zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval -zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval -zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval -zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval -zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval -zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval -zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval -zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval -zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval -zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval -zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval -zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval -zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval -zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval -zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval +zmm0, Class=RegSIMD|Zmmword, 0, 0, 21, 17 +zmm1, Class=RegSIMD|Zmmword, 0, 1, 22, 18 +zmm2, Class=RegSIMD|Zmmword, 0, 2, 23, 19 +zmm3, Class=RegSIMD|Zmmword, 0, 3, 24, 20 +zmm4, Class=RegSIMD|Zmmword, 0, 4, 25, 21 +zmm5, Class=RegSIMD|Zmmword, 0, 5, 26, 22 +zmm6, Class=RegSIMD|Zmmword, 0, 6, 27, 23 +zmm7, Class=RegSIMD|Zmmword, 0, 7, 28, 24 +zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, 25 +zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, 26 +zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, 27 +zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, 28 +zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, 29 +zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, 30 +zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, 31 +zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, 32 +zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, 67 +zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, 68 +zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, 69 +zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, 70 +zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, 71 +zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, 72 +zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, 73 +zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, 74 +zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, 75 +zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, 76 +zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, 77 +zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, 78 +zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, 79 +zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, 80 +zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, 81 +zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, 82 // TMM registers for AMX tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 0a51346eca9..2646f7c3caa 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -44665,259 +44665,259 @@ static const reg_entry i386_regtab[] = { "ymm0", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 0, { Dw2Inval, Dw2Inval } }, + 0, 0, { 21, 17 } }, { "ymm1", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 1, { Dw2Inval, Dw2Inval } }, + 0, 1, { 22, 18 } }, { "ymm2", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 2, { Dw2Inval, Dw2Inval } }, + 0, 2, { 23, 19 } }, { "ymm3", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 3, { Dw2Inval, Dw2Inval } }, + 0, 3, { 24, 20 } }, { "ymm4", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 4, { Dw2Inval, Dw2Inval } }, + 0, 4, { 25, 21 } }, { "ymm5", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 5, { Dw2Inval, Dw2Inval } }, + 0, 5, { 26, 22 } }, { "ymm6", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 6, { Dw2Inval, Dw2Inval } }, + 0, 6, { 27, 23 } }, { "ymm7", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - 0, 7, { Dw2Inval, Dw2Inval } }, + 0, 7, { 28, 24 } }, { "ymm8", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 0, { Dw2Inval, Dw2Inval } }, + RegRex, 0, { Dw2Inval, 25 } }, { "ymm9", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 1, { Dw2Inval, Dw2Inval } }, + RegRex, 1, { Dw2Inval, 26 } }, { "ymm10", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 2, { Dw2Inval, Dw2Inval } }, + RegRex, 2, { Dw2Inval, 27 } }, { "ymm11", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 3, { Dw2Inval, Dw2Inval } }, + RegRex, 3, { Dw2Inval, 28 } }, { "ymm12", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 4, { Dw2Inval, Dw2Inval } }, + RegRex, 4, { Dw2Inval, 29 } }, { "ymm13", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 5, { Dw2Inval, Dw2Inval } }, + RegRex, 5, { Dw2Inval, 30 } }, { "ymm14", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 6, { Dw2Inval, Dw2Inval } }, + RegRex, 6, { Dw2Inval, 31 } }, { "ymm15", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegRex, 7, { Dw2Inval, Dw2Inval } }, + RegRex, 7, { Dw2Inval, 32 } }, { "ymm16", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 0, { Dw2Inval, Dw2Inval } }, + RegVRex, 0, { Dw2Inval, 67 } }, { "ymm17", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 1, { Dw2Inval, Dw2Inval } }, + RegVRex, 1, { Dw2Inval, 68 } }, { "ymm18", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 2, { Dw2Inval, Dw2Inval } }, + RegVRex, 2, { Dw2Inval, 69 } }, { "ymm19", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 3, { Dw2Inval, Dw2Inval } }, + RegVRex, 3, { Dw2Inval, 70 } }, { "ymm20", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 4, { Dw2Inval, Dw2Inval } }, + RegVRex, 4, { Dw2Inval, 71 } }, { "ymm21", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 5, { Dw2Inval, Dw2Inval } }, + RegVRex, 5, { Dw2Inval, 72 } }, { "ymm22", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 6, { Dw2Inval, Dw2Inval } }, + RegVRex, 6, { Dw2Inval, 73 } }, { "ymm23", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex, 7, { Dw2Inval, Dw2Inval } }, + RegVRex, 7, { Dw2Inval, 74 } }, { "ymm24", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 0, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 0, { Dw2Inval, 75 } }, { "ymm25", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 1, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 1, { Dw2Inval, 76 } }, { "ymm26", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 2, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 2, { Dw2Inval, 77 } }, { "ymm27", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 3, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 3, { Dw2Inval, 78 } }, { "ymm28", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 4, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 4, { Dw2Inval, 79 } }, { "ymm29", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 5, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 5, { Dw2Inval, 80 } }, { "ymm30", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 6, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 6, { Dw2Inval, 81 } }, { "ymm31", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, - RegVRex|RegRex, 7, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 7, { Dw2Inval, 82 } }, { "zmm0", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 0, { Dw2Inval, Dw2Inval } }, + 0, 0, { 21, 17 } }, { "zmm1", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 1, { Dw2Inval, Dw2Inval } }, + 0, 1, { 22, 18 } }, { "zmm2", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 2, { Dw2Inval, Dw2Inval } }, + 0, 2, { 23, 19 } }, { "zmm3", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 3, { Dw2Inval, Dw2Inval } }, + 0, 3, { 24, 20 } }, { "zmm4", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 4, { Dw2Inval, Dw2Inval } }, + 0, 4, { 25, 21 } }, { "zmm5", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 5, { Dw2Inval, Dw2Inval } }, + 0, 5, { 26, 22 } }, { "zmm6", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 6, { Dw2Inval, Dw2Inval } }, + 0, 6, { 27, 23 } }, { "zmm7", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - 0, 7, { Dw2Inval, Dw2Inval } }, + 0, 7, { 28, 24 } }, { "zmm8", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 0, { Dw2Inval, Dw2Inval } }, + RegRex, 0, { Dw2Inval, 25 } }, { "zmm9", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 1, { Dw2Inval, Dw2Inval } }, + RegRex, 1, { Dw2Inval, 26 } }, { "zmm10", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 2, { Dw2Inval, Dw2Inval } }, + RegRex, 2, { Dw2Inval, 27 } }, { "zmm11", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 3, { Dw2Inval, Dw2Inval } }, + RegRex, 3, { Dw2Inval, 28 } }, { "zmm12", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 4, { Dw2Inval, Dw2Inval } }, + RegRex, 4, { Dw2Inval, 29 } }, { "zmm13", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 5, { Dw2Inval, Dw2Inval } }, + RegRex, 5, { Dw2Inval, 30 } }, { "zmm14", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 6, { Dw2Inval, Dw2Inval } }, + RegRex, 6, { Dw2Inval, 31 } }, { "zmm15", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegRex, 7, { Dw2Inval, Dw2Inval } }, + RegRex, 7, { Dw2Inval, 32 } }, { "zmm16", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 0, { Dw2Inval, Dw2Inval } }, + RegVRex, 0, { Dw2Inval, 67 } }, { "zmm17", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 1, { Dw2Inval, Dw2Inval } }, + RegVRex, 1, { Dw2Inval, 68 } }, { "zmm18", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 2, { Dw2Inval, Dw2Inval } }, + RegVRex, 2, { Dw2Inval, 69 } }, { "zmm19", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 3, { Dw2Inval, Dw2Inval } }, + RegVRex, 3, { Dw2Inval, 70 } }, { "zmm20", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 4, { Dw2Inval, Dw2Inval } }, + RegVRex, 4, { Dw2Inval, 71 } }, { "zmm21", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 5, { Dw2Inval, Dw2Inval } }, + RegVRex, 5, { Dw2Inval, 72 } }, { "zmm22", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 6, { Dw2Inval, Dw2Inval } }, + RegVRex, 6, { Dw2Inval, 73 } }, { "zmm23", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex, 7, { Dw2Inval, Dw2Inval } }, + RegVRex, 7, { Dw2Inval, 74 } }, { "zmm24", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 0, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 0, { Dw2Inval, 75 } }, { "zmm25", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 1, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 1, { Dw2Inval, 76 } }, { "zmm26", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 2, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 2, { Dw2Inval, 77 } }, { "zmm27", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 3, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 3, { Dw2Inval, 78 } }, { "zmm28", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 4, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 4, { Dw2Inval, 79 } }, { "zmm29", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 5, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 5, { Dw2Inval, 80 } }, { "zmm30", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 6, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 6, { Dw2Inval, 81 } }, { "zmm31", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, - RegVRex|RegRex, 7, { Dw2Inval, Dw2Inval } }, + RegVRex|RegRex, 7, { Dw2Inval, 82 } }, { "tmm0", { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } }, -- 2.39.5