From a7823576f7f7b1cb0a595332ab6b0b38e15f45a7 Mon Sep 17 00:00:00 2001 From: Unnathi Chalicheemala Date: Fri, 31 May 2024 09:45:28 -0700 Subject: [PATCH] arm64: dts: qcom: sm8650: Add Broadcast_AND register in LLCC block Chipsets before SM8450 have only one broadcast register (Broadcast_OR) which is used to broadcast writes and check for status bit 0 only in all channels. >From SM8450 onwards, a new Broadcast_AND region was added which checks for status bit 1. This hasn't been updated and Broadcast_OR region was wrongly being used to check for status bit 1 all along. Hence mapping Broadcast_AND region's address space to LLCC in SM8650. Signed-off-by: Unnathi Chalicheemala Link: https://lore.kernel.org/r/3a8804b35f44485637398faa9c0bda76813fe4d7.1717014052.git.quic_uchalich@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 336c54242778b..bb0b3c48ee4bd 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -4994,12 +4994,14 @@ <0 0x25400000 0 0x200000>, <0 0x25200000 0 0x200000>, <0 0x25600000 0 0x200000>, - <0 0x25800000 0 0x200000>; + <0 0x25800000 0 0x200000>, + <0 0x25a00000 0 0x200000>; reg-names = "llcc0_base", "llcc1_base", "llcc2_base", "llcc3_base", - "llcc_broadcast_base"; + "llcc_broadcast_base", + "llcc_broadcast_and_base"; interrupts = ; }; -- 2.39.5