From a9f99e78e4690d676396fe37e35179fb7edca725 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Fri, 9 Jan 2004 15:49:29 +0000 Subject: [PATCH] re PR target/13380 (An unrecognized insn.) PR target/13380. * gcc.c-torture/compile/20040109-1.c: New. From-SVN: r75587 --- gcc/testsuite/ChangeLog | 5 ++++ .../gcc.c-torture/compile/20040109-1.c | 25 +++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 gcc/testsuite/gcc.c-torture/compile/20040109-1.c diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index dd32bd96ec41..6b905bc442b7 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2004-01-09 Kazu Hirata + + PR target/13380. + * gcc.c-torture/compile/20040109-1.c: New. + 2004-01-08 Stuart Hastings * testsuite/gcc.dg/20020523-2.c (bail_if_no_sse): Moved cpu-ID code... diff --git a/gcc/testsuite/gcc.c-torture/compile/20040109-1.c b/gcc/testsuite/gcc.c-torture/compile/20040109-1.c new file mode 100644 index 000000000000..028bd17c0705 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/20040109-1.c @@ -0,0 +1,25 @@ +/* PR target/13380. + On m32r, the condition code register, (reg:SI 17), was replaced with + a pseudo reg, which would cause an unrecognized insn. */ + +void +foo (unsigned int a, unsigned int b) +{ + if (a > b) + { + while (a) + { + switch (b) + { + default: + a = 0; + case 2: + a = 0; + case 1: + a = 0; + case 0: + ; + } + } + } +} -- 2.47.3