From ab6879f3e997aa966027105487d595ecf46b84a8 Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Mon, 22 Sep 2025 17:29:21 +0100 Subject: [PATCH] arm: fix target-specific test duplicates for gcc This patch fixes all the duplicates that I see when testing GCC (C code). Some of these were real problems with the testsuite where we were testing the wrong thing because of typos; others are due to laxity in the tests so that we had a degree of ambiguity in the results. I've mostly fixed the latter category by converting the relevant test into a check-function-bodies test. gcc/testsuite/ChangeLog: * gcc.target/arm/acle/simd32.c (test_sadd16): Scan for sadd16. * gcc.target/arm/armv8_2-fp16-neon-1.c (vcgtz, 128-bit): Scan for vcgt. * gcc.target/arm/armv8_2-fp16-neon-2.c (vcgtz, 128-bit): Scan for vcgt. (vmul, vmul N): Use check function bodies to avoid ambiguity. * gcc.target/arm/armv8_2-fp16-scalar-1.c (vrndm): Scan for vrintm. (vrndn): Scan for vrintn. (vrndp): Scan for vrintp. (vrndx): Scan for vrintx. * gcc.target/arm/asm-flag-1.c: Scan for movlt. * gcc.target/arm/csneg.c: Convert to check-function-bodies. * gcc.target/arm/mve/dlstp-compile-asm-2.c (test10): Fix comment that caused test9 scan to be run twice. * gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c: Convert to check-function-bodies. * gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c: Likewise. --- gcc/testsuite/gcc.target/arm/acle/simd32.c | 2 +- .../gcc.target/arm/armv8_2-fp16-neon-1.c | 2 +- .../gcc.target/arm/armv8_2-fp16-neon-2.c | 63 ++++++++++++------- .../gcc.target/arm/armv8_2-fp16-scalar-1.c | 8 +-- gcc/testsuite/gcc.target/arm/asm-flag-1.c | 2 +- gcc/testsuite/gcc.target/arm/csneg.c | 33 ++++++++-- .../gcc.target/arm/mve/dlstp-compile-asm-2.c | 3 +- .../arm/mve/intrinsics/vgetq_lane_f16.c | 33 ++++++++-- .../arm/mve/intrinsics/vgetq_lane_f32.c | 33 ++++++++-- .../arm/mve/intrinsics/vgetq_lane_s16.c | 31 +++++++-- .../arm/mve/intrinsics/vgetq_lane_s32.c | 31 +++++++-- .../arm/mve/intrinsics/vgetq_lane_s8.c | 31 +++++++-- .../arm/mve/intrinsics/vgetq_lane_u16.c | 31 +++++++-- .../arm/mve/intrinsics/vgetq_lane_u32.c | 31 +++++++-- .../arm/mve/intrinsics/vgetq_lane_u8.c | 31 +++++++-- 15 files changed, 297 insertions(+), 68 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/acle/simd32.c b/gcc/testsuite/gcc.target/arm/acle/simd32.c index d9b337da35ba..50f7e775fd27 100644 --- a/gcc/testsuite/gcc.target/arm/acle/simd32.c +++ b/gcc/testsuite/gcc.target/arm/acle/simd32.c @@ -315,7 +315,7 @@ test_sadd16 (int16x2_t a, int16x2_t b) return __sadd16 (a, b); } -/* { dg-final { scan-assembler-times "\tsadd8\t...?, ...?, ...?" 1 } } */ +/* { dg-final { scan-assembler-times "\tsadd16\t...?, ...?, ...?" 1 } } */ int16x2_t test_sasx (int16x2_t a, int16x2_t b) diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c index 4cdee1f4ca70..d32c723e5e3e 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-1.c @@ -142,7 +142,7 @@ VCMP1_TEST (vceqz) VCMP1_TEST (vcgtz) /* { dg-final { scan-assembler-times {vcgt\.f16\td[0-9]+, d[0-9]+, #0} 1 } } */ -/* { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, #0} 1 } } */ +/* { dg-final { scan-assembler-times {vcgt\.f16\tq[0-9]+, q[0-9]+, #0} 1 } } */ VCMP1_TEST (vcgez) /* { dg-final { scan-assembler-times {vcge\.f16\td[0-9]+, d[0-9]+, #0} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c index d65f68774616..9e783046d2b4 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-neon-2.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_2a_fp16_neon_ok } */ /* { dg-options "-O2 -ffast-math" } */ /* { dg-add-options arm_v8_2a_fp16_neon } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ /* Test instructions generated for the FP16 vector intrinsics with -ffast-math */ @@ -143,7 +144,7 @@ VCMP1_TEST (vceqz) VCMP1_TEST (vcgtz) /* { dg-final { scan-assembler-times {vcgt\.f16\td[0-9]+, d[0-9]+, #0} 1 } } */ -/* { dg-final { scan-assembler-times {vceq\.f16\tq[0-9]+, q[0-9]+, #0} 1 } } */ +/* { dg-final { scan-assembler-times {vcgt\.f16\tq[0-9]+, q[0-9]+, #0} 1 } } */ VCMP1_TEST (vcgez) /* { dg-final { scan-assembler-times {vcge\.f16\td[0-9]+, d[0-9]+, #0} 1 } } */ @@ -187,43 +188,35 @@ VCVT_N_TEST (vcvt, _u16_f16, uint, float) VCVT_TEST (vcvta, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvta\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvta\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvta\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvta, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvta\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvta\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvta\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtm, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvtm\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtm\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtm\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtm, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvtm\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtm\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtm\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtn, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvtn\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtn\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtn\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtn, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvtn\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtn\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtn\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtp, _s16_f16, int, float) /* { dg-final { scan-assembler-times {vcvtp\.s16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtp\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtp\.s16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ VCVT_TEST (vcvtp, _u16_f16, uint, float) /* { dg-final { scan-assembler-times {vcvtp\.u16\.f16\td[0-9]+, d[0-9]+} 1 } } - { dg-final { scan-assembler-times {vcvtp\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } -*/ + { dg-final { scan-assembler-times {vcvtp\.u16\.f16\tq[0-9]+, q[0-9]+} 1 } } */ UNOP_TEST (vabs) /* { dg-final { scan-assembler-times {vabs\.f16\td[0-9]+, d[0-9]+} 1 } } @@ -326,14 +319,42 @@ BINOP_TEST (vminnm) { dg-final { scan-assembler-times {vminnm\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 1 } } */ BINOP_TEST (vmul) -/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 3 } } - { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } } */ +/* +** test_vmul_16x4: +** ... +** vmul\.f16 d[0-9]+, d[0-9]+, d[0-9]+ +** ... +*/ +/* +** test_vmul_16x8: +** ... +** vmul\.f16 q[0-9]+, q[0-9]+, q[0-9]+ +** ... +*/ BINOP_LANE_TEST (vmul, 2) /* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+\[2\]} 1 } } { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, d[0-9]+\[2\]} 1 } } */ BINOP_N_TEST (vmul) -/* { dg-final { scan-assembler-times {vmul\.f16\td[0-9]+, d[0-9]+, d[0-9]+} 3 } } - { dg-final { scan-assembler-times {vmul\.f16\tq[0-9]+, q[0-9]+, q[0-9]+} 2 } }*/ +/* +** test_vmul_n_16x4: +** ... +** vdup\.f?16 d[0-9]+, .+ +** ... +** vmul\.f16 d[0-9]+, d[0-9]+, d[0-9]+ +** ... +*/ +/* +** test_vmul_n_16x8: +** ... +** ( +** vdup\.f?16 q[0-9]+, .+ +** | +** vld1.16 {d[0-9]+\[\], d[0-9]+\[\]}, \[(sp|r[0-9]+)\] +** ) +** ... +** vmul\.f16 q[0-9]+, q[0-9]+, q[0-9]+ +** ... +*/ float16x4_t test_vpadd_16x4 (float16x4_t a, float16x4_t b) diff --git a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-1.c b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-1.c index 2eddb76f7f42..7340eebf1337 100644 --- a/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-1.c +++ b/gcc/testsuite/gcc.target/arm/armv8_2-fp16-scalar-1.c @@ -164,16 +164,16 @@ UNOP_TEST (vrnda) /* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */ UNOP_TEST (vrndm) -/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vrintm\.f16\ts[0-9]+, s[0-9]+} 1 } } */ UNOP_TEST (vrndn) -/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vrintn\.f16\ts[0-9]+, s[0-9]+} 1 } } */ UNOP_TEST (vrndp) -/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vrintp\.f16\ts[0-9]+, s[0-9]+} 1 } } */ UNOP_TEST (vrndx) -/* { dg-final { scan-assembler-times {vrinta\.f16\ts[0-9]+, s[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vrintx\.f16\ts[0-9]+, s[0-9]+} 1 } } */ UNOP_TEST (vsqrt) /* { dg-final { scan-assembler-times {vsqrt\.f16\ts[0-9]+, s[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c index 97104d3ac73a..0ecab616efe9 100644 --- a/gcc/testsuite/gcc.target/arm/asm-flag-1.c +++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c @@ -32,6 +32,6 @@ void f(char *out) /* { dg-final { scan-assembler "movhi" } } */ /* { dg-final { scan-assembler "movls" } } */ /* { dg-final { scan-assembler "movge" } } */ -/* { dg-final { scan-assembler "movls" } } */ +/* { dg-final { scan-assembler "movlt" } } */ /* { dg-final { scan-assembler "movgt" } } */ /* { dg-final { scan-assembler "movle" } } */ diff --git a/gcc/testsuite/gcc.target/arm/csneg.c b/gcc/testsuite/gcc.target/arm/csneg.c index cf3df13e7e4c..b542f43134a8 100644 --- a/gcc/testsuite/gcc.target/arm/csneg.c +++ b/gcc/testsuite/gcc.target/arm/csneg.c @@ -2,33 +2,54 @@ /* { dg-require-effective-target arm_arch_v8_1m_main_ok } */ /* { dg-options "-O2" } */ /* { dg-add-options arm_arch_v8_1m_main } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ +/* +** test_csneg32_condasn1: +** cmp\tr0, r1 +** csneg\tr0, r3, r2, ne +** bx\tlr +*/ int test_csneg32_condasn1(int w0, int w1, int w2, int w3) { int w4; - - /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*ne" } } */ w4 = (w0 == w1) ? -w2 : w3; return w4; } +/* +** test_csneg32_condasn2: +** cmp\tr0, r1 +** csneg\tr0, r3, r2, eq +** bx\tlr +*/ int test_csneg32_condasn2(int w0, int w1, int w2, int w3) { int w4; - - /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*eq" } } */ w4 = (w0 == w1) ? w3 : -w2; return w4; } +/* +** test_csneg_uxtw: { target arm_little_endian } +** cmp\tr0, #0 +** csneg\tr0, r1, r2, ne +** movs\tr1, #0 +** bx\tlr +*/ +/* +** test_csneg_uxtw: { target { ! arm_little_endian } } +** cmp\tr0, #0 +** csneg\tr1, r1, r2, ne +** movs\tr0, #0 +** bx\tlr +*/ unsigned long long test_csneg_uxtw (unsigned int a, unsigned int b, unsigned int c) { unsigned int val; - - /* { dg-final { scan-assembler "csneg\tr\[0-9\]*.*ne" } } */ val = a ? b : -c; return val; } diff --git a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c index 210930447084..37c54f22abc3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c +++ b/gcc/testsuite/gcc.target/arm/mve/dlstp-compile-asm-2.c @@ -326,8 +326,7 @@ void test10 (int32_t *a, int32_t *b, int32_t *c, int n) } /* We don't need that extra vctp in the loop, but we currently do not optimize - it away, however, it is not wrong to use it... -*/ + it away, however, it is not wrong to use it... */ /* ** test10: **... diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c index a92e1d47393a..b0811372dc71 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,37 @@ foo (float16x8_t a) { return vgetq_lane_f16 (a, 1); } - -/* { dg-final { scan-assembler "vmov.u16" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v8hf +** vmov\td[0-9]+, r2, r3 +** vmov\.u16\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.u16\t(r[0-9]+), q0\[1\] +** vmov\.f16\ts0, \1\t@ __fp16 +** ) +** bx\tlr +*/ float16_t foo1 (float16x8_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.u16" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v8hf +** vmov\td[0-9]+, r2, r3 +** vmov\.u16\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.u16\t(r[0-9]+), q0\[1\] +** vmov\.f16\ts0, \1\t@ __fp16 +** ) +** bx\tlr +*/ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c index 98319eff5c0f..c923b9ecf260 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,37 @@ foo (float32x4_t a) { return vgetq_lane_f32 (a, 1); } - -/* { dg-final { scan-assembler "vmov.32" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v4sf +** vmov\td[0-9]+, r2, r3 +** vmov\.32\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.32\t(r[0-9]+), q0\[1\] +** vmov\ts0, \1 +** ) +** bx\tlr +*/ float32_t foo1 (float32x4_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.32" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v4sf +** vmov\td[0-9]+, r2, r3 +** vmov\.32\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.32\t(r[0-9]+), q0\[1\] +** vmov\ts0, \1 +** ) +** bx\tlr +*/ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c index c9eefeb9972e..4a8963744f8f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,35 @@ foo (int16x8_t a) { return vgetq_lane_s16 (a, 1); } - -/* { dg-final { scan-assembler "vmov.s16" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v8hi +** vmov\td[0-9]+, r2, r3 +** vmov\.s16\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.s16\tr0, q0\[1\] +** ) +** bx\tlr +*/ int16_t foo1 (int16x8_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.s16" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v8hi +** vmov\td[0-9]+, r2, r3 +** vmov\.s16\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.s16\tr0, q0\[1\] +** ) +** bx\tlr +*/ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c index 0925a25bb45d..3a504e84382e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,35 @@ foo (int32x4_t a) { return vgetq_lane_s32 (a, 1); } - -/* { dg-final { scan-assembler "vmov.32" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v4si +** vmov\td[0-9]+, r2, r3 +** vmov\.32\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.32\tr0, q0\[1\] +** ) +** bx\tlr +*/ int32_t foo1 (int32x4_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.32" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v4si +** vmov\td[0-9]+, r2, r3 +** vmov\.32\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.32\tr0, q0\[1\] +** ) +** bx\tlr +*/ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c index 5b76e3da5562..cd014b288774 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,35 @@ foo (int8x16_t a) { return vgetq_lane_s8 (a, 1); } - -/* { dg-final { scan-assembler "vmov.s8" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v16qi +** vmov\td[0-9]+, r2, r3 +** vmov\.s8\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.s8\tr0, q0\[1\] +** ) +** bx\tlr +*/ int8_t foo1 (int8x16_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.s8" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v16qi +** vmov\td[0-9]+, r2, r3 +** vmov\.s8\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.s8\tr0, q0\[1\] +** ) +** bx\tlr +*/ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c index c4a3fb0d3794..74b734051d41 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,35 @@ foo (uint16x8_t a) { return vgetq_lane_u16 (a, 1); } - -/* { dg-final { scan-assembler "vmov.u16" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v8hi +** vmov\td[0-9]+, r2, r3 +** vmov\.u16\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.u16\tr0, q0\[1\] +** ) +** bx\tlr +*/ uint16_t foo1 (uint16x8_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.u16" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v8hi +** vmov\td[0-9]+, r2, r3 +** vmov\.u16\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.u16\tr0, q0\[1\] +** ) +** bx\tlr +*/ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c index d79837023248..c4460e44b9ab 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,35 @@ foo (uint32x4_t a) { return vgetq_lane_u32 (a, 1); } - -/* { dg-final { scan-assembler "vmov.32" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v4si +** vmov\td[0-9]+, r2, r3 +** vmov\.32\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.32\tr0, q0\[1\] +** ) +** bx\tlr +*/ uint32_t foo1 (uint32x4_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.32" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v4si +** vmov\td[0-9]+, r2, r3 +** vmov\.32\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.32\tr0, q0\[1\] +** ) +** bx\tlr +*/ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c index 631d995dc17f..f3abf1e9c566 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c @@ -2,6 +2,7 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ #include "arm_mve.h" @@ -10,13 +11,35 @@ foo (uint8x16_t a) { return vgetq_lane_u8 (a, 1); } - -/* { dg-final { scan-assembler "vmov.u8" } } */ +/* +** foo: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v16qi +** vmov\td[0-9]+, r2, r3 +** vmov\.u8\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.u8\tr0, q0\[1\] +** ) +** bx\tlr +*/ uint8_t foo1 (uint8x16_t a) { return vgetq_lane (a, 1); } - -/* { dg-final { scan-assembler "vmov.u8" } } */ +/* +** foo1: +** ( + -mfloat-abi=softfp +** vmov\td[0-9]+, r0, r1 @ v16qi +** vmov\td[0-9]+, r2, r3 +** vmov\.u8\tr0, q[0-7]\[1\] +** | + -mfloat-abi=hard +** vmov\.u8\tr0, q0\[1\] +** ) +** bx\tlr +*/ -- 2.47.3