From acedbff0f0de1c116a0f8d943c4cf005f61f6143 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 16 May 2025 15:32:16 +0200 Subject: [PATCH] spi: sh-msiof: Correct SIMDR2_GRPMASK The Group Output Mask is not a single bit, but a bit field, containing one bit for each of the four possible groups. Correct the definition. Note that this change has no direct impact, as the driver only uses the first group. Signed-off-by: Geert Uytterhoeven Link: https://patch.msgid.link/ad268d67807cb7e544eddaf7a056793482a965d4.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown --- drivers/spi/spi-sh-msiof.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c index 812e64ea5f79c..57f27040b0fc7 100644 --- a/drivers/spi/spi-sh-msiof.c +++ b/drivers/spi/spi-sh-msiof.c @@ -102,7 +102,7 @@ struct sh_msiof_spi_priv { /* SITMDR2 and SIRMDR2 */ #define SIMDR2_BITLEN1 GENMASK(28, 24) /* Data Size (8-32 bits) */ #define SIMDR2_WDLEN1 GENMASK(23, 16) /* Word Count (1-64/256 (SH, A1))) */ -#define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ +#define SIMDR2_GRPMASK GENMASK(3, 0) /* Group Output Mask 1-4 (SH, A1) */ /* SITSCR and SIRSCR */ #define SISCR_BRPS GENMASK(12, 8) /* Prescaler Setting (1-32) */ @@ -400,7 +400,7 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) sh_msiof_write(p, SITMDR2, dr2); else - sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1); + sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK); if (rx_buf) sh_msiof_write(p, SIRMDR2, dr2); -- 2.39.5