From acf1d51342ee975342c948543cc6129f73f4de70 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Tue, 14 Feb 2012 08:36:16 -0800 Subject: [PATCH] delete arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch --- ...sable-preemption-when-reading-ccsidr.patch | 58 ------------------- queue-3.0/series | 1 - ...sable-preemption-when-reading-ccsidr.patch | 58 ------------------- queue-3.2/series | 1 - 4 files changed, 118 deletions(-) delete mode 100644 queue-3.0/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch delete mode 100644 queue-3.2/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch diff --git a/queue-3.0/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch b/queue-3.0/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch deleted file mode 100644 index 4da1428ddf8..00000000000 --- a/queue-3.0/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch +++ /dev/null @@ -1,58 +0,0 @@ -From b46c0f74657d1fe1c1b0c1452631cc38a9e6987f Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 7 Feb 2012 19:42:07 +0100 -Subject: ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR - -From: Stephen Boyd - -commit b46c0f74657d1fe1c1b0c1452631cc38a9e6987f upstream. - -armv7's flush_cache_all() flushes caches via set/way. To -determine the cache attributes (line size, number of sets, -etc.) the assembly first writes the CSSELR register to select a -cache level and then reads the CCSIDR register. The CSSELR register -is banked per-cpu and is used to determine which cache level CCSIDR -reads. If the task is migrated between when the CSSELR is written and -the CCSIDR is read the CCSIDR value may be for an unexpected cache -level (for example L1 instead of L2) and incorrect cache flushing -could occur. - -Disable interrupts across the write and read so that the correct -cache attributes are read and used for the cache flushing -routine. We disable interrupts instead of disabling preemption -because the critical section is only 3 instructions and we want -to call v7_dcache_flush_all from __v7_setup which doesn't have a -full kernel stack with a struct thread_info. - -This fixes a problem we see in scm_call() when flush_cache_all() -is called from preemptible context and sometimes the L2 cache is -not properly flushed out. - -Signed-off-by: Stephen Boyd -Acked-by: Catalin Marinas -Reviewed-by: Nicolas Pitre -Signed-off-by: Russell King -Signed-off-by: Greg Kroah-Hartman - ---- - arch/arm/mm/cache-v7.S | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -54,9 +54,15 @@ loop1: - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache -+#ifdef CONFIG_PREEMPT -+ save_and_disable_irqs r9 @ make cssr&csidr read atomic -+#endif - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - isb @ isb to sych the new cssr&csidr - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr -+#ifdef CONFIG_PREEMPT -+ restore_irqs_notrace r9 -+#endif - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff diff --git a/queue-3.0/series b/queue-3.0/series index 23608af66eb..16c4e897ba4 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -7,5 +7,4 @@ relay-prevent-integer-overflow-in-relay_open.patch mac80211-timeout-a-single-frame-in-the-rx-reorder-buffer.patch writeback-fix-dereferencing-null-bdi-dev-on-trace_writeback_queue.patch gpio-pca953x-fix-warning-of-enabled-interrupts-in-handler.patch -arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch hwmon-f75375s-fix-automatic-pwm-mode-setting-for-f75373-f75375.patch diff --git a/queue-3.2/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch b/queue-3.2/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch deleted file mode 100644 index 4da1428ddf8..00000000000 --- a/queue-3.2/arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch +++ /dev/null @@ -1,58 +0,0 @@ -From b46c0f74657d1fe1c1b0c1452631cc38a9e6987f Mon Sep 17 00:00:00 2001 -From: Stephen Boyd -Date: Tue, 7 Feb 2012 19:42:07 +0100 -Subject: ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDR - -From: Stephen Boyd - -commit b46c0f74657d1fe1c1b0c1452631cc38a9e6987f upstream. - -armv7's flush_cache_all() flushes caches via set/way. To -determine the cache attributes (line size, number of sets, -etc.) the assembly first writes the CSSELR register to select a -cache level and then reads the CCSIDR register. The CSSELR register -is banked per-cpu and is used to determine which cache level CCSIDR -reads. If the task is migrated between when the CSSELR is written and -the CCSIDR is read the CCSIDR value may be for an unexpected cache -level (for example L1 instead of L2) and incorrect cache flushing -could occur. - -Disable interrupts across the write and read so that the correct -cache attributes are read and used for the cache flushing -routine. We disable interrupts instead of disabling preemption -because the critical section is only 3 instructions and we want -to call v7_dcache_flush_all from __v7_setup which doesn't have a -full kernel stack with a struct thread_info. - -This fixes a problem we see in scm_call() when flush_cache_all() -is called from preemptible context and sometimes the L2 cache is -not properly flushed out. - -Signed-off-by: Stephen Boyd -Acked-by: Catalin Marinas -Reviewed-by: Nicolas Pitre -Signed-off-by: Russell King -Signed-off-by: Greg Kroah-Hartman - ---- - arch/arm/mm/cache-v7.S | 6 ++++++ - 1 file changed, 6 insertions(+) - ---- a/arch/arm/mm/cache-v7.S -+++ b/arch/arm/mm/cache-v7.S -@@ -54,9 +54,15 @@ loop1: - and r1, r1, #7 @ mask of the bits for current cache only - cmp r1, #2 @ see what cache we have at this level - blt skip @ skip if no cache, or just i-cache -+#ifdef CONFIG_PREEMPT -+ save_and_disable_irqs r9 @ make cssr&csidr read atomic -+#endif - mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr - isb @ isb to sych the new cssr&csidr - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr -+#ifdef CONFIG_PREEMPT -+ restore_irqs_notrace r9 -+#endif - and r2, r1, #7 @ extract the length of the cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff diff --git a/queue-3.2/series b/queue-3.2/series index 567aa920130..820e0bf4fdf 100644 --- a/queue-3.2/series +++ b/queue-3.2/series @@ -14,5 +14,4 @@ relay-prevent-integer-overflow-in-relay_open.patch mac80211-timeout-a-single-frame-in-the-rx-reorder-buffer.patch writeback-fix-null-bdi-dev-in-trace-writeback_single_inode.patch writeback-fix-dereferencing-null-bdi-dev-on-trace_writeback_queue.patch -arm-7321-1-cache-v7-disable-preemption-when-reading-ccsidr.patch hwmon-f75375s-fix-automatic-pwm-mode-setting-for-f75373-f75375.patch -- 2.47.3