From ad6b59f058dd31cf3394d4973faf8a636bf60a0c Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Sun, 1 May 2022 20:29:47 +0200 Subject: [PATCH] 5.10-stable patches added patches: iocost-don-t-reset-the-inuse-weight-of-under-weighted-debtors.patch riscv-patch_text-fixup-last-cpu-should-be-master.patch x86-pci-xen-disable-pci-msi-masking-for-xen_hvm-guests.patch --- ...use-weight-of-under-weighted-debtors.patch | 63 +++++++++++++++++++ ...text-fixup-last-cpu-should-be-master.patch | 39 ++++++++++++ queue-5.10/series | 3 + ...e-pci-msi-masking-for-xen_hvm-guests.patch | 57 +++++++++++++++++ 4 files changed, 162 insertions(+) create mode 100644 queue-5.10/iocost-don-t-reset-the-inuse-weight-of-under-weighted-debtors.patch create mode 100644 queue-5.10/riscv-patch_text-fixup-last-cpu-should-be-master.patch create mode 100644 queue-5.10/x86-pci-xen-disable-pci-msi-masking-for-xen_hvm-guests.patch diff --git a/queue-5.10/iocost-don-t-reset-the-inuse-weight-of-under-weighted-debtors.patch b/queue-5.10/iocost-don-t-reset-the-inuse-weight-of-under-weighted-debtors.patch new file mode 100644 index 00000000000..59e42649b75 --- /dev/null +++ b/queue-5.10/iocost-don-t-reset-the-inuse-weight-of-under-weighted-debtors.patch @@ -0,0 +1,63 @@ +From 8c936f9ea11ec4e35e288810a7503b5c841a355f Mon Sep 17 00:00:00 2001 +From: Tejun Heo +Date: Tue, 26 Apr 2022 19:01:01 -1000 +Subject: iocost: don't reset the inuse weight of under-weighted debtors + +From: Tejun Heo + +commit 8c936f9ea11ec4e35e288810a7503b5c841a355f upstream. + +When an iocg is in debt, its inuse weight is owned by debt handling and +should stay at 1. This invariant was broken when determining the amount of +surpluses at the beginning of donation calculation - when an iocg's +hierarchical weight is too low, the iocg is excluded from donation +calculation and its inuse is reset to its active regardless of its +indebtedness, triggering warnings like the following: + + WARNING: CPU: 5 PID: 0 at block/blk-iocost.c:1416 iocg_kick_waitq+0x392/0x3a0 + ... + RIP: 0010:iocg_kick_waitq+0x392/0x3a0 + Code: 00 00 be ff ff ff ff 48 89 4d a8 e8 98 b2 70 00 48 8b 4d a8 85 c0 0f 85 4a fe ff ff 0f 0b e9 43 fe ff ff 0f 0b e9 4d fe ff ff <0f> 0b e9 50 fe ff ff e8 a2 ae 70 00 66 90 0f 1f 44 00 00 55 48 89 + RSP: 0018:ffffc90000200d08 EFLAGS: 00010016 + ... + + ioc_timer_fn+0x2e0/0x1470 + call_timer_fn+0xa1/0x2c0 + ... + +As this happens only when an iocg's hierarchical weight is negligible, its +impact likely is limited to triggering the warnings. Fix it by skipping +resetting inuse of under-weighted debtors. + +Signed-off-by: Tejun Heo +Reported-by: Rik van Riel +Fixes: c421a3eb2e27 ("blk-iocost: revamp debt handling") +Cc: stable@vger.kernel.org # v5.10+ +Link: https://lore.kernel.org/r/YmjODd4aif9BzFuO@slm.duckdns.org +Signed-off-by: Jens Axboe +Signed-off-by: Greg Kroah-Hartman +--- + block/blk-iocost.c | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +--- a/block/blk-iocost.c ++++ b/block/blk-iocost.c +@@ -2257,7 +2257,17 @@ static void ioc_timer_fn(struct timer_li + iocg->hweight_donating = hwa; + iocg->hweight_after_donation = new_hwi; + list_add(&iocg->surplus_list, &surpluses); +- } else { ++ } else if (!iocg->abs_vdebt) { ++ /* ++ * @iocg doesn't have enough to donate. Reset ++ * its inuse to active. ++ * ++ * Don't reset debtors as their inuse's are ++ * owned by debt handling. This shouldn't affect ++ * donation calculuation in any meaningful way ++ * as @iocg doesn't have a meaningful amount of ++ * share anyway. ++ */ + TRACE_IOCG_PATH(inuse_shortage, iocg, &now, + iocg->inuse, iocg->active, + iocg->hweight_inuse, new_hwi); diff --git a/queue-5.10/riscv-patch_text-fixup-last-cpu-should-be-master.patch b/queue-5.10/riscv-patch_text-fixup-last-cpu-should-be-master.patch new file mode 100644 index 00000000000..3be63f8b2e3 --- /dev/null +++ b/queue-5.10/riscv-patch_text-fixup-last-cpu-should-be-master.patch @@ -0,0 +1,39 @@ +From 8ec1442953c66a1d8462cccd8c20b7ba561f5915 Mon Sep 17 00:00:00 2001 +From: Guo Ren +Date: Wed, 6 Apr 2022 22:16:49 +0800 +Subject: riscv: patch_text: Fixup last cpu should be master + +From: Guo Ren + +commit 8ec1442953c66a1d8462cccd8c20b7ba561f5915 upstream. + +These patch_text implementations are using stop_machine_cpuslocked +infrastructure with atomic cpu_count. The original idea: When the +master CPU patch_text, the others should wait for it. But current +implementation is using the first CPU as master, which couldn't +guarantee the remaining CPUs are waiting. This patch changes the +last CPU as the master to solve the potential risk. + +Signed-off-by: Guo Ren +Signed-off-by: Guo Ren +Acked-by: Palmer Dabbelt +Reviewed-by: Masami Hiramatsu +Fixes: 043cb41a85de ("riscv: introduce interfaces to patch kernel code") +Cc: stable@vger.kernel.org +Signed-off-by: Palmer Dabbelt +Signed-off-by: Greg Kroah-Hartman +--- + arch/riscv/kernel/patch.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/arch/riscv/kernel/patch.c ++++ b/arch/riscv/kernel/patch.c +@@ -100,7 +100,7 @@ static int patch_text_cb(void *data) + struct patch_insn *patch = data; + int ret = 0; + +- if (atomic_inc_return(&patch->cpu_count) == 1) { ++ if (atomic_inc_return(&patch->cpu_count) == num_online_cpus()) { + ret = + patch_text_nosync(patch->addr, &patch->insn, + GET_INSN_LENGTH(patch->insn)); diff --git a/queue-5.10/series b/queue-5.10/series index 6dc323a62ed..c8f6df40019 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -32,3 +32,6 @@ arch_topology-do-not-set-llc_sibling-if-llc_id-is-invalid.patch pinctrl-samsung-fix-missing-gpiolib-on-arm64-exynos-config.patch hex2bin-make-the-function-hex_to_bin-constant-time.patch hex2bin-fix-access-beyond-string-end.patch +riscv-patch_text-fixup-last-cpu-should-be-master.patch +x86-pci-xen-disable-pci-msi-masking-for-xen_hvm-guests.patch +iocost-don-t-reset-the-inuse-weight-of-under-weighted-debtors.patch diff --git a/queue-5.10/x86-pci-xen-disable-pci-msi-masking-for-xen_hvm-guests.patch b/queue-5.10/x86-pci-xen-disable-pci-msi-masking-for-xen_hvm-guests.patch new file mode 100644 index 00000000000..0454659c9da --- /dev/null +++ b/queue-5.10/x86-pci-xen-disable-pci-msi-masking-for-xen_hvm-guests.patch @@ -0,0 +1,57 @@ +From 7e0815b3e09986d2fe651199363e135b9358132a Mon Sep 17 00:00:00 2001 +From: Thomas Gleixner +Date: Thu, 28 Apr 2022 15:50:54 +0200 +Subject: x86/pci/xen: Disable PCI/MSI[-X] masking for XEN_HVM guests + +From: Thomas Gleixner + +commit 7e0815b3e09986d2fe651199363e135b9358132a upstream. + +When a XEN_HVM guest uses the XEN PIRQ/Eventchannel mechanism, then +PCI/MSI[-X] masking is solely controlled by the hypervisor, but contrary to +XEN_PV guests this does not disable PCI/MSI[-X] masking in the PCI/MSI +layer. + +This can lead to a situation where the PCI/MSI layer masks an MSI[-X] +interrupt and the hypervisor grants the write despite the fact that it +already requested the interrupt. As a consequence interrupt delivery on the +affected device is not happening ever. + +Set pci_msi_ignore_mask to prevent that like it's done for XEN_PV guests +already. + +Fixes: 809f9267bbab ("xen: map MSIs into pirqs") +Reported-by: Jeremi Piotrowski +Reported-by: Dusty Mabe +Reported-by: Salvatore Bonaccorso +Signed-off-by: Thomas Gleixner +Tested-by: Noah Meyerhans +Cc: stable@vger.kernel.org +Link: https://lore.kernel.org/r/87tuaduxj5.ffs@tglx +Signed-off-by: Greg Kroah-Hartman +--- + arch/x86/pci/xen.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/arch/x86/pci/xen.c ++++ b/arch/x86/pci/xen.c +@@ -476,7 +476,6 @@ static __init void xen_setup_pci_msi(voi + xen_msi_ops.setup_msi_irqs = xen_setup_msi_irqs; + } + xen_msi_ops.teardown_msi_irqs = xen_pv_teardown_msi_irqs; +- pci_msi_ignore_mask = 1; + } else if (xen_hvm_domain()) { + xen_msi_ops.setup_msi_irqs = xen_hvm_setup_msi_irqs; + xen_msi_ops.teardown_msi_irqs = xen_teardown_msi_irqs; +@@ -490,6 +489,11 @@ static __init void xen_setup_pci_msi(voi + * in allocating the native domain and never use it. + */ + x86_init.irqs.create_pci_msi_domain = xen_create_pci_msi_domain; ++ /* ++ * With XEN PIRQ/Eventchannels in use PCI/MSI[-X] masking is solely ++ * controlled by the hypervisor. ++ */ ++ pci_msi_ignore_mask = 1; + } + + #else /* CONFIG_PCI_MSI */ -- 2.47.3