From aee63b07fd1c2316d96dff0a6217288a630ce147 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Mon, 7 Jan 2019 15:23:46 +0000 Subject: [PATCH] hw/arm: versal: Plug memory leaks MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Plug a couple of "board creation time" memory leaks. Fixes: 6f16da53ffe4567 ("hw/arm: versal: Add a virtual Xilinx Versal board") Reported-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-id: 20190104104749.5314-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal-virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index c6feeac532f..f95fde2309b 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -130,6 +130,7 @@ static void fdt_add_gic_nodes(VersalVirt *s) 2, MM_GIC_APU_REDIST_0_SIZE); qemu_fdt_setprop_cell(s->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "arm,gic-v3"); + g_free(nodename); } static void fdt_add_timer_nodes(VersalVirt *s) @@ -364,6 +365,7 @@ static void create_virtio_regions(VersalVirt *s) sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq); mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_add_subregion(&s->soc.mr_ps, base, mr); + g_free(name); } for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) { -- 2.39.5